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HGT1S12N60B3DS9A PDF预览

HGT1S12N60B3DS9A

更新时间: 2024-02-09 00:42:18
品牌 Logo 应用领域
其他 - ETC 晶体晶体管电动机控制瞄准线双极性晶体管
页数 文件大小 规格书
7页 206K
描述
TRANSISTOR | IGBT | N-CHAN | 600V V(BR)CES | 12A I(C) | TO-263AB

HGT1S12N60B3DS9A 技术参数

生命周期:Transferred包装说明:SMALL OUTLINE, R-PSSO-G2
Reach Compliance Code:unknown风险等级:5.57
Is Samacsys:N其他特性:LOW CONDUCTION LOSS, HYPER FAST RECOVERY
外壳连接:COLLECTOR最大集电极电流 (IC):27 A
集电极-发射极最大电压:600 V配置:SINGLE WITH BUILT-IN DIODE
JEDEC-95代码:TO-263ABJESD-30 代码:R-PSSO-G2
元件数量:1端子数量:2
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE极性/信道类型:N-CHANNEL
认证状态:Not Qualified表面贴装:YES
端子形式:GULL WING端子位置:SINGLE
晶体管应用:MOTOR CONTROL晶体管元件材料:SILICON
标称断开时间 (toff):280 ns标称接通时间 (ton):22 ns
Base Number Matches:1

HGT1S12N60B3DS9A 数据手册

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HGTG12N60B3D, HGTP12N60B3D, HGT1S12N60B3DS  
Test Circuit and Waveform  
HGTP12N60B3D  
90%  
OFF  
10%  
ON  
V
GE  
E
E
L = 1mH  
V
CE  
R
= 25Ω  
G
90%  
10%  
d(OFF)I  
+
I
CE  
t
t
V
= 480V  
rI  
DD  
t
fI  
-
t
d(ON)I  
FIGURE 19. INDUCTIVE SWITCHING TEST CIRCUIT  
FIGURE 20. SWITCHING TEST WAVEFORM  
Handling Precautions for IGBTs  
Operating Frequency Information  
Insulated Gate Bipolar Transistors are susceptible to  
gate insulation damage by the electrostatic discharge of  
energy through the devices. When handling these devices,  
care should be exercised to assure that the static charge  
built in the handler’s body capacitance is not discharged  
through the device. With proper handling and application  
procedures, however, IGBTs are currently being extensively  
used in production by numerous equipment manufacturers in  
military, industrial and consumer applications, with virtually  
no damage problems due to electrostatic discharge. IGBTs  
can be handled safely if the following basic precautions are  
taken:  
Operating frequency information for a typical device  
(Figure 3) is presented as a guide for estimating device  
performance for a specific application. Other typical  
frequency vs collector current (I ) plots are possible using  
CE  
the information shown for a typical unit in Figures 5, 6, 7, 8, 9  
and 11. The operating frequency plot (Figure 3) of a typical  
device shows f  
or f ; whichever is smaller at each  
MAX1  
MAX2  
point. The information is based on measurements of a  
typical device and is bounded by the maximum rated  
junction temperature.  
f
is defined by f  
= 0.05/(t  
MAX1  
+ t ).  
d(OFF)I d(ON)I  
MAX1  
Deadtime (the denominator) has been arbitrarily held to 10%  
of the on-state time for a 50% duty factor. Other definitions  
1. Prior to assembly into a circuit, all leads should be kept  
shorted together either by the use of metal shorting  
springs or by the insertion into conductive material such  
as “ECCOSORBD™ LD26” or equivalent.  
are possible. t  
and t are defined in Figure 20.  
d(OFF)I  
d(ON)I  
Device turn-off delay can establish an additional frequency  
limiting condition for an application other than T . t  
JM d(OFF)I  
2. When devices are removed by hand from their carriers,  
the hand being used should be grounded by any suitable  
means - for example, with a metallic wristband.  
is important when controlling output ripple under a lightly  
loaded condition.  
f
is defined by f  
MAX2  
= (P - P )/(E  
OFF  
+ E ). The  
ON  
MAX2  
D
C
3. Tips of soldering irons should be grounded.  
allowable dissipation (P ) is defined by P = (T - T )/R  
.
D
D
JM θJC  
C
4. Devices should never be inserted into or removed from  
circuits with power on.  
The sum of device switching and conduction losses must not  
exceed P . A 50% duty factor was used (Figure 3) and the  
D
5. Gate Voltage Rating - Never exceed the gate-voltage  
conduction losses (PC) are approximated by  
rating of V  
. Exceeding the rated V can result in  
GEM  
GE  
P
= (V  
CE  
x I )/2.  
CE  
permanent damage to the oxide layer in the gate region.  
C
6. Gate Termination - The gates of these devices are  
essentially capacitors. Circuits that leave the gate open-  
circuited or floating should be avoided. These conditions  
can result in turn-on of the device due to voltage buildup  
on the input capacitor due to leakage currents or pickup.  
E
and E  
are defined in the switching waveforms  
OFF  
ON  
shown in Figure 20. E  
is the integral of the instantaneous  
ON  
power loss (I  
CE  
x V ) during turn-on and E  
is the  
OFF  
x V ) during  
CE  
integral of the instantaneous power loss (I  
CE  
CE  
turn-off. All tail losses are included in the calculation for  
; i.e., the collector current equals zero (I = 0).  
7. Gate Protection - These devices do not have an internal  
monolithic Zener diode from gate to emitter. If gate  
protection is required an external Zener is recommended.  
E
OFF  
CE  
©2001 Fairchild Semiconductor Corporation  
HGTG12N60B3D, HGTP12N60B3D, HGT1S12N60B3DS Rev. B  

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