Datasheet > HD74CDC2509

HD74CDC2509

更新时间： 2024-11-21 21:18:35

品牌	Logo	应用领域
瑞萨 - RENESAS		驱动光电二极管逻辑集成电路
页数	文件大小	规格书
11页	52K
描述
CDC SERIES, PLL BASED CLOCK DRIVER, PDSO24, TTP-24DB

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HD74CDC2509 技术参数

生命周期：	Transferred	零件包装代码：	SOIC
包装说明：	TSSOP,	针数：	24
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.58	系列：	CDC
JESD-30 代码：	R-PDSO-G24	长度：	7.8 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	端子数量：	24
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSSOP
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态：	Not Qualified	座面最大高度：	1.1 mm
表面贴装：	YES	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
宽度：	4.4 mm	Base Number Matches：	1

HD74CDC2509 数据手册

HD74CDC2509

3.3-V Phase-lock Loop Clock Driver

Preliminary

1st. Edition

December 1997

Description

The HD74CDC2509 is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a

phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the

clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The

HD74CDC2509 operates at 3.3 V V_CCand is designed to drive up to five clock loads per output.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of the input

clock. Output signal duty cycles are adjusted to 50 percent independent of the duty cycle at the input clock.

Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the

G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the

outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the HD74CDC2509 does not require external RC networks. The

loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, HD74CDC2509 requires a stabilization time to achieve phase lock of

the feedback signal to the reference signal. This stabilization time is required, following power up and

application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL

reference or feedback signals. The PLL can be bypassed for test purposes by strapping AV_CCto ground.

Features

•

Phase-lock loop clock distribution for synchronous DRAM applications

External feedback (FBIN) pin is used to synchronize the outputs to the clock input

No external RC network required

12 3 4 5 6 7...11

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与HD74CDC2509相关器件

型号	品牌	获取价格	描述	数据表
HD74CDC2509B	RENESAS	获取价格	3.3-V Phase-lock Loop Clock Driver
HD74CDC2509B	HITACHI	获取价格	3.3-V Phase-lock Loop Clock Driver
HD74CDC2509BT	HITACHI	获取价格	PLL Based Clock Driver, CDC Series, 9 True Output(s), 0 Inverted Output(s), PDSO24, TTP-24
HD74CDC2509BTEL	RENESAS	获取价格	3.3-V Phase-lock Loop Clock Driver
HD74CDC2510B	RENESAS	获取价格	3.3-V Phase-lock Loop Clock Driver
HD74CDC2510B	HITACHI	获取价格	3.3-V Phase-lock Loop Clock Driver
HD74CDC2510BT	HITACHI	获取价格	PLL Based Clock Driver, CDC Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TTP-2
HD74CDC2510BTEL	RENESAS	获取价格	3.3-V Phase-lock Loop Clock Driver
HD74CDC587	HITACHI	获取价格	PLL Based Clock Driver, CDC Series, CMOS, PDSO56, TTP-56D
HD74CDC857	HITACHI	获取价格	3.3/2.5-V Phase-lock Loop Clock Driver

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