Datasheet > HD74CDC857

HD74CDC857

更新时间： 2024-10-04 22:37:03

品牌	Logo	应用领域
日立 - HITACHI		时钟驱动器
页数	文件大小	规格书
12页	56K
描述
3.3/2.5-V Phase-lock Loop Clock Driver

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HD74CDC857 数据手册

HD74CDC857

3.3/2.5-V Phase-lock Loop Clock Driver

ADE-205-222E (Z)

6th. Edition

July 1999

Description

The HD74CDC857 is a high-performance, low-skew, low-jitter, phase locked loop clock driver. It is

specifically designed for use with DDR (Double Data Rate) synchronous DRAMs.

Features

•

Supports 100 MHz to 150 MHz operation range ^*1

Distributes one differential clock input pair to ten differential clock outputs pairs

SSTL_2 (Stub Series Terminated Logic) differential inputs and LVCMOS reset (G) input

Supports spread spectrum clock

External feedback pins (FBIN, FBIN) are used to synchronize the outputs to the clock input

Supports both 3.3 V/2.5V analog supply voltage (AV_CC), and 2.5 V V_DDQ

No external RC network required

Sleep mode detection

48pin TSSOP (Thin Shrink Small Outline Package)

Note: 1. 200 MHz (Max) ver. will be available by 4Q/’99

Function Table

Inputs

Outputs

PLL

CLK

FBOUT FBOUT

off

run

off

0 MHz

H :

L :

Z :

X :

High level

Low level

High impedance

Don’t care

12 3 4 5 6 7...12

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