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HD74CDCV857AT PDF预览

HD74CDCV857AT

更新时间: 2024-10-05 12:58:35
品牌 Logo 应用领域
瑞萨 - RENESAS 时钟驱动器
页数 文件大小 规格书
13页 221K
描述
CDCV SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, TSSOP-48

HD74CDCV857AT 技术参数

生命周期:Not Recommended零件包装代码:TSSOP
包装说明:TSSOP,针数:48
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.7Is Samacsys:N
系列:CDCV输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G48长度:12.5 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:48
实输出次数:10最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.1 ns座面最大高度:1.2 mm
最大供电电压 (Vsup):2.7 V最小供电电压 (Vsup):2.3 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
宽度:6.1 mm最小 fmax:170 MHz
Base Number Matches:1

HD74CDCV857AT 数据手册

 浏览型号HD74CDCV857AT的Datasheet PDF文件第2页浏览型号HD74CDCV857AT的Datasheet PDF文件第3页浏览型号HD74CDCV857AT的Datasheet PDF文件第4页浏览型号HD74CDCV857AT的Datasheet PDF文件第5页浏览型号HD74CDCV857AT的Datasheet PDF文件第6页浏览型号HD74CDCV857AT的Datasheet PDF文件第7页 
HD74CDCV857  
2.5-V Phase-lock Loop Clock Driver  
REJ03D0135–0700Z  
(Previous ADE-205-335E (Z))  
Preliminary  
Rev.7.00  
Oct.09.2003  
Description  
The HD74CDCV857 is a high-performance, low-skew, low-jitter, phase clock driver. It is  
specifically designed for use with DDR (Double Data Rate) synchron
Features  
DDR266 / PC2100-Compliant  
Supports 60 MHz to 170 MHz operation range  
Distributes one differential clock input pair to ten s  
Supports spread spectrum clock requirements egistered DIMM  
specification  
External feedback pins (FBIN, FBIN) auts to the clock input  
Supports 2.5V analog supply voltag
No external RC network required  
Sleep mode detection  
48pin TSSOP (Thin Shrink
Function Table  
Inputs  
:
PLL  
AVCC  
GND  
GND  
X
PWR
L
Y
H
L
Z
Z
L
L
Z
FBOUT FBOUT  
H
H
L
:
:
:
:
:
L
H
L
Z
Z
L
L
Z
:
:
:
:
:
:
:
Bypassed / off *1  
Bypassed / off *1  
L
H
Z
Z
H
H
Z
H
Z
Z
H
H
Z
off  
off  
on  
on  
off  
X
L
H
L
2.5 V  
2.5 V  
2.5 V  
H
H
X
H
L
H
0 MHz 0 MHz  
H :  
L :  
X :  
Z :  
High level  
Low level  
Don’t care  
High impedance  
Note: 1. Bypasse mode is used for RENESAS test mode.  
Rev.7.00, Oct.09.2003, page 1 of 12  

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