HD74CDCF2509BTEL

更新时间： 2024-10-05 05:35:11

品牌	Logo	应用领域
瑞萨 - RENESAS		时钟驱动器逻辑集成电路光电二极管
页数	文件大小	规格书
9页	218K
描述
140 MHz, 0 to 85°C Operation 3.3-V Phase-lock Loop Clock Driver

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

HD74CDCF2509BTEL 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	TSSOP	包装说明：	TSSOP, TSSOP24,.25
针数：	24	Reach Compliance Code：	unknown
HTS代码：	8542.39.00.01	风险等级：	5.65
Is Samacsys：	N	系列：	CDCF
输入调节：	STANDARD	JESD-30 代码：	R-PDSO-G24
长度：	7.8 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
最大I（ol）：	0.012 A	功能数量：	1
反相输出次数：		端子数量：	24
实输出次数：	9	最高工作温度：	85 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装等效代码：	TSSOP24,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：	3.3 V	认证状态：	Not Qualified
Same Edge Skew-Max（tskwd）：	0.15 ns	座面最大高度：	1.1 mm
子类别：	Clock Drivers	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	OTHER
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	宽度：	4.4 mm
Base Number Matches：	1

HD74CDCF2509BTEL 数据手册

HD74CDCF2509B

140 MHz, 0 to 85°C Operation

3.3-V Phase-lock Loop Clock Driver

REJ03D0827-1000

(Previous: ADE-205-224H)

Rev.10.00

Apr 07, 2006

Description

The HD74CDCF2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock

loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input

signal. It is specifically designed for use with synchronous DRAMs. The HD74CDCF2509B operates at 3.3 V V_CCand

is designed to drive up to five clock loads per output.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of the input clock.

Output signal duty cycles are adjusted to 50 percent independent of the duty cycle at the input clock. Each bank of

outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the

outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low

state.

Unlike many products containing PLLs, the HD74CDCF2509B does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, HD74CDCF2509B requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required, following power up and application of a

fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals.

Features

•

Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1”

Phase-lock loop clock distribution for synchronous DRAM applications

External feedback (FBIN) pin is used to synchronize the outputs to the clock input

No external RC network required

Support spread spectrum clock (SSC) synthesizers

Supports frequencies up to 140 MHz

0 to 85°C operating range

Ordering Information

Package Code

(Previous code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

Part Name

Package Type

HD74CDCF2509BTEL TSSOP-24 pin

PTSP0024JB-A

(TTP-24DBV)

EL (1,000 pcs / Reel)

Rev.10.00 Apr 07, 2006 page 1 of 8

12 3 4 5 6 7...9

中文翻译

下载PDF

与HD74CDCF2509BTEL相关器件

型号	品牌	获取价格	描述	数据表
HD74CDCF2510B	HITACHI	获取价格	140 MHz, 0 to 85∑C Operation 3.3-V Phase-lock
HD74CDCF2510BT	HITACHI	获取价格	PLL Based Clock Driver, CDCF Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TTP-
HD74CDCF2510BTEL	HITACHI	获取价格	PLL Based Clock Driver, CDCF Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TTP-
HD74CDCF2510BTEL	RENESAS	获取价格	CDCF SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, 4.40
HD74CDCV851	ETC	获取价格	Datasheet\|ADE-205-653F\|DEC.26.02\|88K
HD74CDCV852	ETC	获取价格	Datasheet\|ADE-205-675C\|DEC.26.02\|81K
HD74CDCV857	HITACHI	获取价格	2.5-V Phase-lock Loop Clock Driver
HD74CDCV857	RENESAS	获取价格	2.5-V Phase-lock Loop Clock Driver
HD74CDCV857A	RENESAS	获取价格	2.5-V Phase-lock Loop Clock Driver
HD74CDCV857AT	RENESAS	获取价格	CDCV SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48, TSSO

与HD74CDCF2509BTEL相关文章

晶圆厂易主：Coherent公司2000万英镑出售苹果供应链关键资产
2024-10-08

6
Galaxy S25系列或全系搭载骁龙8 Elite
2024-10-08

4
三大厂商12层HBM3E进展迅速
2024-10-08

5
塔塔电子与力积电达成技术转让协议，携手建设印度首座晶圆厂
2024-09-29

43

产品中心

服务支持

精选活动

关于我们

帮助中心

HD74CDCF2509BTEL

HD74CDCF2509BTEL 技术参数

HD74CDCF2509BTEL 数据手册

与HD74CDCF2509BTEL相关器件

与HD74CDCF2509BTEL相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

HD74CDCF2509BTEL

HD74CDCF2509BTEL 技术参数

HD74CDCF2509BTEL 数据手册

与HD74CDCF2509BTEL相关器件

与HD74CDCF2509BTEL相关文章

您还可以找

您在本页遇到什么问题？