HD74CDCF2509B

更新时间： 2024-10-04 22:37:03

品牌	Logo	应用领域
日立 - HITACHI		时钟驱动器
页数	文件大小	规格书
11页	43K
描述
140 MHz, 0 to 85∑C Operation 3.3-V Phase-lock Loop Clock Driver

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HD74CDCF2509B 数据手册

HD74CDCF2509B

140 MHz, 0 to 85°C Operation

3.3-V Phase-lock Loop Clock Driver

ADE-205-224F (Z)

7th. Edition

January 2000

Description

The HD74CDCF2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a

phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the

clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The

HD74CDCF2509B operates at 3.3 V V_CCand is designed to drive up to five clock loads per output.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of the input

clock. Output signal duty cycles are adjusted to 50 percent independent of the duty cycle at the input clock.

Each bank of outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the

G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the

outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the HD74CDCF2509B does not require external RC networks.

The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, HD74CDCF2509B requires a stabilization time to achieve phase lock

of the feedback signal to the reference signal. This stabilization time is required, following power up and

application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL

reference or feedback signals. The PLL can be bypassed for test purposes by strapping AV_CCto ground.

Features

•

Supports PC133 and meets “PC SDRAM registered DIMM specification, Rev. 1.1”

Phase-lock loop clock distribution for synchronous DRAM applications

External feedback (FBIN) pin is used to synchronize the outputs to the clock input

No external RC network required

Support spread spectrum clock (SSC) synthesizers

Supports frequencies up to 140 MHz

0 to 85°C operating range

12 3 4 5 6 7...11

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型号	品牌	获取价格	描述	数据表
HD74CDCF2509BT	RENESAS	获取价格	暂无描述
HD74CDCF2509BTEL	RENESAS	获取价格	140 MHz, 0 to 85°C Operation 3.3-V Phase-lock
HD74CDCF2510B	HITACHI	获取价格	140 MHz, 0 to 85∑C Operation 3.3-V Phase-lock
HD74CDCF2510BT	HITACHI	获取价格	PLL Based Clock Driver, CDCF Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TTP-
HD74CDCF2510BTEL	HITACHI	获取价格	PLL Based Clock Driver, CDCF Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TTP-
HD74CDCF2510BTEL	RENESAS	获取价格	CDCF SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, 4.40
HD74CDCV851	ETC	获取价格	Datasheet\|ADE-205-653F\|DEC.26.02\|88K
HD74CDCV852	ETC	获取价格	Datasheet\|ADE-205-675C\|DEC.26.02\|81K
HD74CDCV857	HITACHI	获取价格	2.5-V Phase-lock Loop Clock Driver
HD74CDCV857	RENESAS	获取价格	2.5-V Phase-lock Loop Clock Driver