HD74CDC2510BT

更新时间： 2024-10-05 13:08:15

品牌	Logo	应用领域
日立 - HITACHI		时钟驱动器逻辑集成电路光电二极管
页数	文件大小	规格书
11页	47K
描述
PLL Based Clock Driver, CDC Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TTP-24DB

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HD74CDC2510BT 数据手册

HD74CDC2510B

3.3-V Phase-lock Loop Clock Driver

ADE-205-219F (Z)

7th. Edition

October 1999

Description

The HD74CDC2510B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a

phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the

clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The

HD74CDC2510B operates at 3.3 V V_CCand is designed to drive up to five clock loads per output.

Bank of outputs provide ten low-skew, low-jitter copies of the input clock. Output signal duty cycles are

adjusted to 50 percent independent of the duty cycle at the input clock. Bank of outputs can be enabled or

disabled via the control (G) inputs. When the G inputs are high, the outputs switch in phase and frequency

with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.

Unlike many products containing PLLs, the HD74CDC2510B does not require external RC networks. The

loop filter for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, HD74CDC2510B requires a stabilization time to achieve phase lock

of the feedback signal to the reference signal. This stabilization time is required, following power up and

application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL

reference or feedback signals. The PLL can be bypassed for test purposes by strapping AV_CCto ground.

Features

•

Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”

Phase-lock loop clock distribution for synchronous DRAM applications

External feedback (FBIN) pin is used to synchronize the outputs to the clock input

No external RC network required

Support spread spectrum clock (SSC) synthesizers

Note: Only by a change of a suffix (A to B) for standardization, there isn’t any change of the product.

12 3 4 5 6 7...11

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型号	品牌	获取价格	描述	数据表
HD74CDC2510BTEL	RENESAS	获取价格	3.3-V Phase-lock Loop Clock Driver
HD74CDC587	HITACHI	获取价格	PLL Based Clock Driver, CDC Series, CMOS, PDSO56, TTP-56D
HD74CDC857	HITACHI	获取价格	3.3/2.5-V Phase-lock Loop Clock Driver
HD74CDCF2509B	RENESAS	获取价格	140 MHz, 0 to 85°C Operation 3.3-V Phase-lock
HD74CDCF2509B	HITACHI	获取价格	140 MHz, 0 to 85∑C Operation 3.3-V Phase-lock
HD74CDCF2509BT	RENESAS	获取价格	暂无描述
HD74CDCF2509BTEL	RENESAS	获取价格	140 MHz, 0 to 85°C Operation 3.3-V Phase-lock
HD74CDCF2510B	HITACHI	获取价格	140 MHz, 0 to 85∑C Operation 3.3-V Phase-lock
HD74CDCF2510BT	HITACHI	获取价格	PLL Based Clock Driver, CDCF Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TTP-
HD74CDCF2510BTEL	HITACHI	获取价格	PLL Based Clock Driver, CDCF Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TTP-