Datasheet > HD74CDC587

HD74CDC587

更新时间： 2024-11-11 19:47:19

品牌	Logo	应用领域
日立 - HITACHI		光电二极管
页数	文件大小	规格书
13页	79K
描述
PLL Based Clock Driver, CDC Series, CMOS, PDSO56, TTP-56D

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HD74CDC587 数据手册

HD74CDC587

3.3-V Phase-lock Loop Clock Driver with 3-state Outputs

Preliminary

1st. Edition

September 1997

Description

The HD74CDC587 is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It

uses a PLL to precisely align, in both frequency and phase, the clock output signals to the clock input

(CLKIN) signal. The HD74CDC587 operates at 3.3-V V_CCand provides LVTTL- or SSTL_3- compatible

inputs and outputs. The HD74CDC587 operates at frequencies from 50 MHz up to 150 MHz, and is

ideally suited for high speed microprocessor and synchronous DRAM applications.

A dedicated feedback output (FBOUT) is used to synchronize the output clocks in frequency and phase to

the CLKIN reference. Four banks of four outputs (1Yn, 2Yn, 3Yn, 4Yn) are configured to operate at the

same frequency (1×) as the CLKIN. For proper operation, all SELn (n = 0, 1, 2, 3) inputs must be

externally tied to logic low.

The output enable (OE) input provides control for the Y output banks. When OE is high, the outputs are in

a high impedance state. When OE is low, the outputs switch at (1×) the CLKIN frequency. In addition,

RESET provides a master reset for the HD74CDC587 counter circuitry. This allows the outputs to be reset

to a known state. TEST provides a bypass of the integrated PLL and divider circuitry. When TEST is

high, the input clock bypasses the PLL and is buffered directly to the outputs.

The loop filter components of the PLL are integrated on the HD74CDC587. This reduces the need for

external loop components and provides an easily implemented PLL circuit. FBOUT should be connected

to the feedback input (FBIN) for normal operation of the PLL.

The voltage-controlled oscillator (VCO) of the integrated PLL has an operating range of 100 MHz to 300

MHz. The VCO is designed to operate at twice (2×) the CLKIN frequency. This allows the HD74CDC587

to achieve output frequencies from 50 MHz to 150 MHz with a duty cycle of 50% ±10% ensured.

Independent analog V_CC(AV_CC) and ground (AGND) connections are provided for VCO stability.

CLKIN and FBIN can be configured to switch at SSTL_3 input levels by connecting V_REFto a nominal

reference voltage of 1.5 V. If V_REFis strapped to GND, CLKIN and FBIN switch at normal TTL input

thresholds.

Because the HD74CDC587 is based on PLL technology, it requires a stabilization time to active phase lock

of the FBIN to the reference input clock. This stabilization time is required following power up and

application of a fixed-frequency, fixed-phase signal at CLKIN. In addition, a stabilization time may be

12 3 4 5 6 7...13

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与HD74CDC587相关器件

型号	品牌	获取价格	描述	数据表
HD74CDC857	HITACHI	获取价格	3.3/2.5-V Phase-lock Loop Clock Driver
HD74CDCF2509B	RENESAS	获取价格	140 MHz, 0 to 85°C Operation 3.3-V Phase-lock
HD74CDCF2509B	HITACHI	获取价格	140 MHz, 0 to 85∑C Operation 3.3-V Phase-lock
HD74CDCF2509BT	RENESAS	获取价格	暂无描述
HD74CDCF2509BTEL	RENESAS	获取价格	140 MHz, 0 to 85°C Operation 3.3-V Phase-lock
HD74CDCF2510B	HITACHI	获取价格	140 MHz, 0 to 85∑C Operation 3.3-V Phase-lock
HD74CDCF2510BT	HITACHI	获取价格	PLL Based Clock Driver, CDCF Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TTP-
HD74CDCF2510BTEL	HITACHI	获取价格	PLL Based Clock Driver, CDCF Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TTP-
HD74CDCF2510BTEL	RENESAS	获取价格	CDCF SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, 4.40
HD74CDCV851	ETC	获取价格	Datasheet\|ADE-205-653F\|DEC.26.02\|88K

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