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HD74CDC2509BTEL PDF预览

HD74CDC2509BTEL

更新时间: 2024-11-11 11:04:35
品牌 Logo 应用领域
瑞萨 - RENESAS 时钟驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 223K
描述
3.3-V Phase-lock Loop Clock Driver

HD74CDC2509BTEL 技术参数

生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP,针数:24
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.56系列:CDC
输入调节:STANDARDJESD-30 代码:R-PDSO-G24
长度:7.8 mm逻辑集成电路类型:PLL BASED CLOCK DRIVER
功能数量:1反相输出次数:
端子数量:24实输出次数:9
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
认证状态:Not Qualified座面最大高度:1.1 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:OTHER端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
宽度:4.4 mmBase Number Matches:1

HD74CDC2509BTEL 数据手册

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HD74CDC2509B  
3.3-V Phase-lock Loop Clock Driver  
REJ03D0825-0900  
(Previous: ADE-205-218G)  
Rev.9.00  
Apr 07, 2006  
Description  
The HD74CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock  
loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input  
signal. It is specifically designed for use with synchronous DRAMs. The HD74CDC2509B operates at 3.3 V VCC and  
is designed to drive up to five clock loads per output.  
One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of the input clock.  
Output signal duty cycles are adjusted to 50 percent independent of the duty cycle e input clock. Each bank of  
outputs can be enabled or disabled separately via the control (1G and 2G) inputshe G inputs are high, the  
outputs switch in phase and frequency with CLK; when the G inputs are low, disabled to the logic-low  
state.  
Unlike many products containing PLLs, the HD74CDC2509B does ns. The loop filter  
for the PLL is included on-chip, minimizing component count, boa
Because it is based on PLL circuitry, HD74CDC2509B require phase lock of the  
feedback signal to the reference signal. This stabilization tr up and application of a  
fixed-frequency, fixed-phase signal at CLK, as well as fL reference or feedback signals.  
The PLL can be bypassed for test purposes by strapp
Features  
Meets “PC SDRAM registered DIMM 1.2”  
Phase-lock loop clock distribution ftions  
External feedback (FBIN) pin is s to the clock input  
No external RC network requ
Support spread spectrum
Ordering Information  
Package Code  
(Previous code)  
Package  
Abbreviation  
Taping Abbreviation  
(Quantity)  
Part Name  
HD74CDC2509BTEL  
PTSP0024JB-A  
(TTP-24DBV)  
T
EL (1,000 pcs / Reel)  
*Only by a change of a suffix (A for standardization, there isn’t any change of the product.  
Function Table  
Inputs  
Outputs  
1G  
2G  
X
CLK  
L
1Y (0:4)  
2Y (0:3)  
FBOUT  
X
L
L
L
L
L
L
L
H
H
H
H
H
L
H
L
H
L
H
L
H
H
H
H
H
H
H
H
H :  
L :  
X :  
High level  
Low level  
Immaterial  
Rev.9.00 Apr 07, 2006 page 1 of 7  

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