HD74CDC2509B

更新时间： 2024-10-05 11:04:35

品牌	Logo	应用领域
瑞萨 - RENESAS		时钟驱动器逻辑集成电路光电二极管
页数	文件大小	规格书
8页	223K
描述
3.3-V Phase-lock Loop Clock Driver

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技术参数
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HD74CDC2509B 技术参数

生命周期：	Not Recommended	零件包装代码：	SOIC
包装说明：	TSSOP,	针数：	24
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.37	Is Samacsys：	N
系列：	CDC	JESD-30 代码：	R-PDSO-G24
长度：	7.8 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
端子数量：	24	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	认证状态：	Not Qualified
座面最大高度：	1.1 mm	表面贴装：	YES
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	宽度：	4.4 mm
Base Number Matches：	1

HD74CDC2509B 数据手册

HD74CDC2509B

3.3-V Phase-lock Loop Clock Driver

REJ03D0825-0900

(Previous: ADE-205-218G)

Rev.9.00

Apr 07, 2006

Description

The HD74CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop clock driver. It uses a phase-lock

loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input

signal. It is specifically designed for use with synchronous DRAMs. The HD74CDC2509B operates at 3.3 V V_CCand

is designed to drive up to five clock loads per output.

One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of the input clock.

Output signal duty cycles are adjusted to 50 percent independent of the duty cycle at the input clock. Each bank of

outputs can be enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the

outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low

state.

Unlike many products containing PLLs, the HD74CDC2509B does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, HD74CDC2509B requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required, following power up and application of a

fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals.

The PLL can be bypassed for test purposes by strapping AV_CCto ground.

Features

•

Meets “PC SDRAM registered DIMM design support document, Rev. 1.2”

Phase-lock loop clock distribution for synchronous DRAM applications

External feedback (FBIN) pin is used to synchronize the outputs to the clock input

No external RC network required

Support spread spectrum clock (SSC) synthesizers

Ordering Information

Package Code

(Previous code)

Package

Abbreviation

Taping Abbreviation

(Quantity)

Part Name

HD74CDC2509BTEL

Package Type

TSSOP-24 pin

PTSP0024JB-A

(TTP-24DBV)

EL (1,000 pcs / Reel)

*Only by a change of a suffix (A to B) for standardization, there isn’t any change of the product.

Function Table

Inputs

Outputs

CLK

1Y (0:4)

2Y (0:3)

FBOUT

H :

L :

X :

High level

Low level

Immaterial

Rev.9.00 Apr 07, 2006 page 1 of 7

12 3 4 5 6 7 8

中文翻译

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与HD74CDC2509B相关器件

型号	品牌	获取价格	描述	数据表
HD74CDC2509BT	HITACHI	获取价格	PLL Based Clock Driver, CDC Series, 9 True Output(s), 0 Inverted Output(s), PDSO24, TTP-24
HD74CDC2509BTEL	RENESAS	获取价格	3.3-V Phase-lock Loop Clock Driver
HD74CDC2510B	RENESAS	获取价格	3.3-V Phase-lock Loop Clock Driver
HD74CDC2510B	HITACHI	获取价格	3.3-V Phase-lock Loop Clock Driver
HD74CDC2510BT	HITACHI	获取价格	PLL Based Clock Driver, CDC Series, 10 True Output(s), 0 Inverted Output(s), PDSO24, TTP-2
HD74CDC2510BTEL	RENESAS	获取价格	3.3-V Phase-lock Loop Clock Driver
HD74CDC587	HITACHI	获取价格	PLL Based Clock Driver, CDC Series, CMOS, PDSO56, TTP-56D
HD74CDC857	HITACHI	获取价格	3.3/2.5-V Phase-lock Loop Clock Driver
HD74CDCF2509B	RENESAS	获取价格	140 MHz, 0 to 85°C Operation 3.3-V Phase-lock
HD74CDCF2509B	HITACHI	获取价格	140 MHz, 0 to 85∑C Operation 3.3-V Phase-lock

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