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GD16555B/155-68AB PDF预览

GD16555B/155-68AB

更新时间： 2024-11-12 20:00:27
品牌 Logo 应用领域
英特尔 - INTEL ATM异步传输模式
页数 文件大小 规格书
20页 247K
描述
ATM/SONET/SDH IC, Bipolar, PQFP68,

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中文翻译

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GD16555B/155-68AB 技术参数

是否Rohs认证： 不符合生命周期：Active
包装说明：QFF, QFL68,.75SQ,40Reach Compliance Code：compliant
风险等级：5.45JESD-30 代码：S-PQFP-F68
JESD-609代码：e0负电源额定电压：-5.2 V
端子数量：68封装主体材料：PLASTIC/EPOXY
封装代码：QFF封装等效代码：QFL68,.75SQ,40
封装形状：SQUARE封装形式：FLATPACK
电源：-5.2 V认证状态：Not Qualified
子类别：ATM/SONET/SDH ICs最大压摆率：480 mA
表面贴装：YES技术：BIPOLAR
端子面层：Tin/Lead (Sn/Pb)端子形式：FLAT
端子节距：1 mm端子位置：QUAD
Base Number Matches：1

GD16555B/155-68AB 数据手册

 浏览型号GD16555B/155-68AB的Datasheet PDF文件第2页浏览型号GD16555B/155-68AB的Datasheet PDF文件第3页浏览型号GD16555B/155-68AB的Datasheet PDF文件第4页浏览型号GD16555B/155-68AB的Datasheet PDF文件第5页浏览型号GD16555B/155-68AB的Datasheet PDF文件第6页浏览型号GD16555B/155-68AB的Datasheet PDF文件第7页 
10 Gbit/s  
Transmitter MUX  
with Re-timing  
GD16555B  
Preliminary  
General Description  
Features  
l
GD16555B is a 9.95328 Gbit/s transmit-  
ter chip for use in SDH STM-64 and  
SONET OC-192 optical communication  
systems.  
The output of the MUX stage is retimed  
by the 10 GHz clock and the output  
driver is a Current Mode Logic (CML)  
output with internal 50 Ω termination re-  
sistors.  
On-chip low noise 10 GHz VCO with  
a wide tuning range.  
l
Automated capture of the VCO  
frequency by a true phase and  
frequency detector.  
GD16555B integrates all the main func-  
tions of the transmitter, which is clock  
generation, PLL circuits and multiplexer  
in a single monolithic IC. Hence only an  
external loop filter is required.  
The 16 bit wide parallel input interface is  
differential CML with 50 Ω internal load  
termination, and with a 622 MHz clock  
output mastering the timing at the STM-4  
interface. The phase of the output clock  
is selected in four phases: 0°, 90°, 180°,  
and 270° by two select pins.  
l
Retiming of MUX stage output with  
10 GHz clock.  
l
Clock failure detection NLDET.  
The main functions of GD16555B are  
shown in the figure below. The clock  
generation is made on-chip by a low  
noise and tuneable 10 GHz VCO. The  
VCO centre frequency is controlled by a  
PLL with an external loop filter, allowing  
the user to control the loop characteristic.  
l
16:1 MUX with differential 622 Mbit/s  
CML data input.  
GD16555B is manufactured in a Silicon  
Bipolar process.  
l
CML data input with 50 Ω internal  
load termination.  
GD16555B uses a single -5.2 V supply  
voltage.  
l
622 MHz clock output for counter  
clocking.  
The clock synchronisation is controlled  
by the Phase and Frequency Detector  
with a 155 MHz or 622 MHz reference  
clock input (package bonding option).  
The power dissipation is 2 W, typical.  
l
Clock output is selectable in four  
phases: 0°, 90°, 180°, or 270°.  
GD16555B is delivered in a Multi Layer  
Ceramic (MLC) package, with internal  
high-speed 50 Ω transmission lines.  
l
GD16555B multiplexes a 16 bit parallel  
622 Mbit/s interface into a serial  
9.9553 Gbit/s data stream.  
155 MHz or 622 MHz reference clock  
input (package bonding option).  
All high-speed signals is bonded with  
GiGA’s proprietary Flexguide® Bonding  
Technique.  
l
Single supply operation: -5.2 V  
l
Low Power dissipation: 2 W (typ.).  
l
Silicon Bipolar process.  
DI0  
DIN0  
FF  
l
68 pin Multi Layer Ceramic (MLC)  
package.  
Flexguide  
OUT  
16:1  
Parallel  
Input Data  
OUTN  
Multiplexer  
l
DI15  
DIN15  
CKOUT  
CKOUTN  
Flexguide® Bonding Technique.  
NLDET  
Timing  
Control  
SEL1  
SEL2  
Phase  
PCLT  
POUT  
Frequency  
Applications  
Detector  
VCO  
PHIGH  
l
VCTL  
Telecommunication systems:  
PLOW  
–
–
SDH STM-64  
SONET OC-192.  
VCUR  
(only /155 vers.)  
l
l
Fibre optic test equipment.  
TCK  
S
E
L
3
(*)  
R
E
F
C
K
R
E
F
C
K
N
VDD VDDO VDDA VEE  
(*) = Package Bonding Option  
Submarime transmission systems.  
1234567...20

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