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GD16557/ECL-100BA PDF预览

GD16557/ECL-100BA

更新时间： 2024-02-29 05:16:55
品牌 Logo 应用领域
英特尔 - INTEL /
页数 文件大小 规格书
28页 225K
描述
Transmitter, 1-Func, PQFP100, HEAT SINK, TQFP-100

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GD16557/ECL-100BA 技术参数

生命周期：Obsolete零件包装代码：QFP
包装说明：HLFQFP, HQFP100,.63SQ,20针数：100
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.84应用程序：SONET;SDH
JESD-30 代码：S-PQFP-G100长度：14 mm
功能数量：1端子数量：100
封装主体材料：PLASTIC/EPOXY封装代码：HLFQFP
封装等效代码：HQFP100,.63SQ,20封装形状：SQUARE
封装形式：FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH电源：3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
子类别：Other Telecom ICs标称供电电压：3.3 V
表面贴装：YES电信集成电路类型：ATM/SONET/SDH TRANSMITTER
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

GD16557/ECL-100BA 数据手册

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2.5 Gbit/s  
Transponder  
Chip Set with  
Digital “Wrapping”  
GD16556/GD16557*  
Preliminary  
General Description  
Features  
The GD16556 and GD16557 constitute a  
high performance multi-bitrate tran-  
sponder chip set designed for Optical  
Network applications. The devices are  
available with either LVDS or LVPECL  
low-speed I/Os.  
system level service purposes. The de-  
vices can operate with STM-1 (OC3),  
STM-4 (OC12), STM-16 (OC48) and  
Gigabit Ethernet line rates multiplied by a  
fraction. Fractions available are 32/31,  
16/15 and 15/14. Thus, for example, data  
might be transmitted (or received) at a  
rate of 32/31 times 2.488 Gbit/s with a  
high- speed clock of 2.568 GHz. The  
fractions are available through selection  
of programmable dividers.  
General  
l
SDH (SONET) STM-1(OC3) /  
STM-4(OC12) / STM-16(OC48) / GE  
compatible  
True on-the-fly multi-bit rate operation  
Bypass for non-compatible bit rates  
Loop-back for system test mode  
Overhead data rate capability  
l
l
l
The chip set is compatible with the line  
rates:  
l
u
SDH STM-1 / SONET OC3  
SDH STM-4 / SONET OC12  
–
–
–
15/14 (7% overhead)  
16/15 (6% overhead)  
32/31 (3% overhead)  
u
u
SDH STM-16 / SONET OC48  
Gigabit Ethernet  
l
l
l
u
Signal Levels and Power Supply  
Low speed interfaces are LVDS/LVPECL  
compatible. The high-speed output from  
the transmitter GD16557 is of CML-type  
(open collector). Select pins are LVTTL  
compatible.  
LVDS/LVPECL low-speed I/O  
Single power supply: +3.3 V  
100 pin TQFP EDQUAD packages  
Switching between the bit rates is possi-  
ble on-the-fly through select pins.  
The chip set is designed for interconnect-  
ing the high-speed line interface to stan-  
dard CMOS ASICs or FPGAs. The  
on-chip VCO and PLL blocks eliminate  
external high-speed clock signals and  
complicated timing relations.  
GD16556 (Receiver)  
Low power consumption is achieved by a  
single +3.3 V power supply and by omit-  
ting all circuitry, which can easily be im-  
plemented in the low speed system  
ASIC.  
l
Clock and Data Recovery  
1:16 Demultiplexer  
Differential input with 5 mVPP  
sensitivity  
Loss of signal monitor  
Bit consecutive monitor  
Lock detect monitor  
Power dissipation: 1.3 W (typ.)  
l
l
l
Digital “Wrapping” Modes  
l
GD16556 and GD16557 are capable of  
transmitting and receiving data at in-  
creased rates if overhead is needed for  
The devices are housed in 100 pin TQFP  
EDQUAD thermal enhanced packages.  
l
l
16  
16  
STM-1 / OC3  
STM-4 / OC12  
STM-16 / OC48  
Gigabit  
STM-1/OC3  
GD16557 (Transmitter)  
GD16557  
Jitter  
Cleaner &  
MUX 16:1  
STM-4/OC12  
STM-16/OC48  
Gigabit  
GD16556  
CDR &  
DeMUX 1:16  
System  
ASIC  
l
16:1 Multiplexer  
Optional double PLL jitter-clean up  
Counter or forward clocked  
low-speed interface  
PLL lock-detect  
Power dissipation: 1.3 W (typ.)  
Ethernet  
Clock  
Clock  
Ethernet  
Times:  
1,  
l
l
15/14,  
16/15,  
32/31  
VCXO  
l
Clock  
Clock  
l
Line  
Side  
System  
Side  
Applications  
16  
16  
STM-1 / OC3  
STM-1/OC3  
STM-4/OC12  
STM-16/OC48  
Gigabit  
STM-4 / OC12  
STM-16 / OC48  
Gigabit  
l
GD16557  
Jitter  
Cleaner &  
MUX 16:1  
Digital “Wrappers”  
Optical Networking  
Transponders  
SDH/SONET FEC out-of-band  
GD16556  
CDR &  
DeMUX 1:16  
System  
ASIC  
l
Ethernet  
l
Clock  
Clock  
Ethernet  
Times:  
1,  
l
15/14,  
16/15,  
32/31  
systems  
Network interconnects  
Gateways  
Datacom  
l
l
Clock  
Clock  
VCXO  
l
*: Patent pending  
Data Sheet Rev.: 19  
1234567...28

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