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GD16588-132EA PDF预览

GD16588-132EA

更新时间： 2024-11-12 14:50:31
品牌 Logo 应用领域
英特尔 - INTEL ATM异步传输模式
页数 文件大小 规格书
13页 161K
描述
ATM/SONET/SDH IC, Bipolar, CBGA132,

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中文翻译

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GD16588-132EA 技术参数

是否Rohs认证：不符合生命周期：Active
包装说明：BGA, BGA132,12X12,40Reach Compliance Code：compliant
风险等级：5.44Is Samacsys：N
JESD-30 代码：S-XBGA-B132JESD-609代码：e0
端子数量：132封装主体材料：CERAMIC
封装代码：BGA封装等效代码：BGA132,12X12,40
封装形状：SQUARE封装形式：GRID ARRAY
电源：3.3,-5.2 V认证状态：Not Qualified
子类别：ATM/SONET/SDH ICs表面贴装：YES
技术：BIPOLAR端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：1 mm
端子位置：BOTTOMBase Number Matches：1

GD16588-132EA 数据手册

 浏览型号GD16588-132EA的Datasheet PDF文件第2页浏览型号GD16588-132EA的Datasheet PDF文件第3页浏览型号GD16588-132EA的Datasheet PDF文件第4页浏览型号GD16588-132EA的Datasheet PDF文件第5页浏览型号GD16588-132EA的Datasheet PDF文件第6页浏览型号GD16588-132EA的Datasheet PDF文件第7页 
10 Gbit/s  
Receiver, CDR and  
DeMUX  
GD16584/GD16588  
(FEC)  
Preliminary  
General Description  
Features  
l
GD16584 and GD16588 are Receiver  
chips for use in STM-64/192 and Optical  
Transport Networking (OTN) systems.  
500 ppm from the reference clock, it  
automatically switches the phase and fre-  
quency detector into the PLL loop. In the  
auto lock mode the locking range is  
selectable between 500 or 2000 ppm.  
Complete Clock and Data Recovery  
IC with auto acquisition.  
l
1:16 DeMUX with differential  
622 Mbit/s data outputs  
The component is available in two ver-  
sions:  
u
l
GD16584 for 9.5328 Gbit/s.  
GD16588 for 10.66 Gbit/s for OTN or  
When the VCO frequency is within the  
lock range, the Bang-Bang Phase Detec-  
tor takes over. It controls the phase of  
the VCO until the sampling point of data  
is in the middle of the bit period, where  
the eye opening is largest. A ±40 mV  
Decision Threshold Control (DTC) is pro-  
vided at the 10 Gbit/s input.  
622 MHz Clock output.  
u
l
Forward Error Correction (FEC).  
Except the different operating bit rates  
the two versions are functional identical.  
LVDS compatible clock and data  
outputs.  
l
OIF99.102.5 compliant timing.  
The receiver is a Clock and Data Reco-  
very IC with:  
l
155 or 622 MHz Reference Clock.  
u
a low noise VCO  
a Bang-Bang Phase Detector  
u
l
The 10 Gbit/s input data is sampled and  
de-multiplexed by the 1:16 DeMUX. The  
parallel output interface is synchronised  
with the 622 MHz output clock. The clock  
and data outputs are LVDS compatible.  
Input Decision Threshold Control  
(DTC): ±40 mV.  
u
a 1:16 De-multiplexer  
a Lock Detect  
a Phase and Frequency Detector.  
u
u
l
Low noise VCO with ±5 % tuning  
range.  
Clock and data are regenerated by using  
a Phase Locked Loop (PLL) with an ex-  
ternal passive loop filter.  
l
The device operates from a dual -5.2 V  
and +3.3 V power supply. The power dis-  
sipation is 3.3 W, typical.  
Dual supply operation: -5.2 V and  
+3.3 V.  
The VCO frequency is controlled by one  
of the two Phase Detectors in order to  
ensure capture and lock to the line data  
rate. The Lock Detector circuit monitors  
the VCO frequency and determines when  
the VCO is within the lock range. When  
the frequency deviates more than  
l
Power dissipation: 3.3 W (typ).  
The device is manufactured in a Silicon  
Bipolar process and packaged in an 132  
balls 13 × 13 mm Ceramic Ball Grid  
Array (CBGA).  
l
Silicon Bipolar technology.  
l
132 balls Ceramic BGA 13 × 13 mm  
package.  
l
VCO  
CKOUT  
CKOUTN  
Available in two versions:  
Timing Control  
VCTL  
–
–
GD16584 for 10 Gbit/s  
GD16588 for 10.66 Gbit/s  
DO0  
DON0  
Parallel  
Output  
Data  
1:16  
DI  
DIN  
Bang  
Bang  
Applications  
Demultiplexer  
Phase  
Detector  
DO15  
DON15  
Decision  
Threshold  
Control  
l
DTC  
Telecommunication systems:  
DTCN  
–
–
–
SDH STM-64  
U
D
SONET OC-192.  
Optical Transport Networking  
(OTN)  
PCTL  
Phase  
Frequency  
Detector  
–
FEC applications  
(PHIGH)  
(PLOW)  
REFCK  
REFCKN  
l
l
Fibre optic test equipment.  
Submarine systems.  
1/4  
Lock  
Detect  
LOCK  
RESET TCK  
SEL3  
SEL1  
SEL2  
VCC  
VDD  
VDDA VDDO  
VEE  
VEEA  
Data Sheet Rev.: 07  
1234567...13

中文翻译

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