10 Gbit/s
Transmitter MUX
with Re-timing
GD16585
Preliminary
General Description
Features
l
GD16585 is a 9.95328 Gbit/s transmitter
chip for use in SDH STM-64 and SONET
OC-192 optical communication systems.
by a second Phase and Frequency De-
tector (PFCX). It compares the input data
clock with the on-chip load clock. The
output of the PFCX is the phase and fre-
quency control of the external VCXO
reference clock.
On-chip low noise VCO with a wide
tuning range.
l
Automated capture of the VCO
frequency by a true phase and
frequency detector.
GD16585 integrates all the main func-
tions of the transmitter, which is clock
generation, PLL circuits and multiplexer
in a single monolithic IC. Hence only an
external loop filter and a VCXO are
required.
l
The output of the MUX stage is retimed
by the 10 GHz clock and the output
driver is a Current Mode Logic (CML)
output with internal 50 Ω termination re-
sistors.
Retiming of MUX stage output with
10 GHz clock.
l
Clock failure detection NLDET.
The main functions of GD16585 are
shown in the figure below. The clock
generation is made on-chip by a low
noise and tuneable 10 GHz VCO. The
VCO frequency is controlled by the PLL
with an external loop filter, allowing the
user to control the loop characteristic.
l
Phase nulling circuit for easy
interfacing with the system ASIC.
The 16 bit wide parallel input interface is
LVDS compatible with a 2 × 50 Ω internal
load termination.
l
16:1 MUX with differential 622 Mbit/s
LVDS data inputs.
GD16585 is manufactured in a Silicon Bi-
polar process.
l
CML data input with 50 Ω internal
load termination.
The clock synchronisation is controlled
by the Phase and Frequency Detector
with a 155 MHz or 622 MHz reference
clock input.
GD16585 uses a -5.2 V supply voltage
and +3.3 V supply for interfacing LVDS.
l
LVDS compatible data and clock
inputs with 100 Ω internal load termi-
nation.
The power dissipation is 2.2 W, typical.
GD16585 multiplexes a 16 bit parallel
622 Mbit/s interface into a serial
9.9553 Gbit/s data stream.
l
GD16585 is delivered in an 132 leads
ceramic Ball Grid Array (BGA). The size
of the package is 13 × 13 mm.
622 MHz clock output for counter
clocking.
l
The timing between the input data and
the on-chip clock system are controlled
155 MHz or 622 MHz reference clock
input (selectable).
l
Dual supply operation: -5.2 V and
+3.3 V
DI0
DIN0
VCUR
FF
l
Low power dissipation: 2.2 W (typ.).
16:1
OUT
OUTN
Parallel
Input Data
Multiplexer
l
Silicon Bipolar process.
DI15
DIN15
l
132 leads ceramic BGA 13 × 13 mm
package.
NLDET
Timing
Control
SEL1
SEL2
Phase
l
Available in two versions:
Selector
Phase
–
–
GD16585 for 10 Gbit/s
GD16589 for 10.66 Gbit/s
CKOUT
CKOUTN
PCTL
Frequency
Detector
PHIGH
PLOW
CKI
CKIN
PFCX
Applications
VCO
l
Telecommunication systems:
–
–
SDH STM-64
SONET OC-192.
TCK
PCTLX
SGNX
VCTL
SEL3
REFCK/N VCC VDD VDDO VDDA VEE
l
Fibre optic test equipment.