STM-4/STM-1/E4
3.3 V Multifunction
Transmitter and
Receiver
an Intel company
GD16591A/GD16592A
General Description
Features
The GD16591A and GD16592A is a
front-end transmitter/receiver chip set de-
signed for multiple line interfaces:
The GD16592A comprises a Limiting In-
put Amplifier (LIA), Clock & Data Recov-
ery, and a configurable DeMUX circuit.
The LIA offers a differential input sensi-
tivity of 10 mV peak to peak for the high-
speed serial input. A Lock Detect output
monitors the PLL locked onto the re-
ceived serial data.
General
l
Low jitter on-chip VCO and PLL.
u
STM-4 / OC-12
STM-1 / OC-3
PDH E4
l
u
Jitter performance exceeds the rec-
ommendations of ITU-T and Bellcore.
u
l
This chip set is designed to interconnect
the high speed line interface to standard
CMOS ASICs providing low speed data
interface.
The chip set offers seven line and
system speed mode:
The low-speed interface I/O´s are
LVTTL-level, and the high-speed I/O´s
are differential LVPECL levels (The LIA
input is usable as LVPECL input).
622 Mbit/s « 78 Mbit/s, 8 bit
311 Mbit/s « 78 Mbit/s, 4 bit
155 Mbit/s « 78 Mbit/s, 2 bit
155 Mbit/s « 19 Mbit/s, 8 bit
280 Mbit/s « 70 Mbit/s, 4 bit
140 Mbit/s « 70 Mbit/s, 2 bit
140 Mbit/s « 17 Mbit/s, 8 bit
The GD16591A and GD16592A devices
are designed for use in both electrical
and optical line interface modules. The
devices support line speeds of:
System (local) Loop-back and Line (re-
mote) Loop-back functions offer simpli-
fied manufacturing and field testing.
l
u
140/155 Mbit/s NRZ mode for E4/
Four phase selectable clock to data
timing at parallel interface.
OC-3/STM-1 for an optical line inter-
face.
280/311 Mbit/s for E4/OC-3/STM-1 in
Low power consumption is achieved by
the 3.3 V single power supply and by
omitting all circuitry, which can easily be
implemented in the low speed system
ASIC, thus reducing the overall power
consumption.
l
u
Selectable reference clock input fre-
quencies:
CMI mode for electrical line interface,
where en-/decoding is made at the
system site.
17.408/19.44MHz, 34.816/
38.88MHz, and 69.632/77.76MHz.
u
622 Mbit/s NRZ mode line speed for
OC-12/STM-4 operation.
l
Loop Back for System & Line test
modes.
The devices are housed in 48 pin
EDQUAD TQFPä plastic packages.
The on-chip VCO and PLL blocks for
clock generation eliminate the need for
an external high-speed clock signal.
l
48 pin EDQUAD TQFPä packages.
l
Single supply: 3.1 ... 3.6 V.
GD16591A
MUX/
Retiming PLL
GD16591A (Transmitter)
CMOS System ASIC
l
8:1 / 4:1 / 2:1 MUX.
Data
70/78 Mbit/s
17/19 Mbit/s
Line Interface
2 / 4 / 8 bit
Clock
140/155 Mbit/s (optical)
280/311 Mbit/s (electrical)
622 Mbit/s (STM-4 opt.)
l
Differential transmitted clock output.
l
LVPECL data outputs.
l
Optional forward/counter clocking
scheme.
System / Line Loop Back
l
Power dissipation, typ.: 350 mW
Data
70/78 Mbit/s
17/19 Mbit/s
Line Interface
2 / 4 / 8 bit
Clock
140/155 Mbit/s (optical)
280/311 Mbit/s (electrical)
622 Mbit/s (STM-4 opt.)
GD16592A (Receiver)
l
1:8 / 1:4 / 1:2 DeMUX.
GD16592A
DeMUX/
CDR with PLL
Data Sheet Rev.: 14