Datasheet > GD16592-48BA

GD16592-48BA

更新时间： 2024-11-11 15:33:03

品牌	Logo	应用领域
英特尔 - INTEL		/
页数	文件大小	规格书
16页	192K
描述
Telecom IC, Bipolar, PQFP48,

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中文翻译

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技术参数
数据手册

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GD16592-48BA 技术参数

是否Rohs认证：	不符合	生命周期：	Active
包装说明：	QFP, QFP48,.35SQ,20	Reach Compliance Code：	compliant
风险等级：	5.22	JESD-30 代码：	S-PQFP-G48
JESD-609代码：	e0	端子数量：	48
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP48,.35SQ,20	封装形状：	SQUARE
封装形式：	FLATPACK	电源：	3.3 V
认证状态：	Not Qualified	子类别：	Other Telecom ICs
最大压摆率：	160 mA	标称供电电压：	3.3 V
表面贴装：	YES	技术：	BIPOLAR
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
Base Number Matches：	1

GD16592-48BA 数据手册

STM-4/STM-1/E4

3.3 V Multifunction

Transmitter and

Receiver

GD16591/GD16592

Preliminary

General Description

Features

The GD16591 and GD16592 is a front-

end transmitter/receiver chip set de-

signed for multiple line interfaces:

The GD16592 comprises a Limiting Input

Amplifier (LIA), Clock & Data Recovery,

and a configurable DeMUX circuit. The

LIA offers a differential input sensitivity of

10 mV peak to peak for the high-speed

serial input. A Lock Detect output moni-

tors the PLL locked onto the received se-

rial data.

General

Low jitter on-chip VCO and PLL.

Jitter performance exceeds the rec-

STM-4 / OC-12

STM-1 / OC-3

PDH E4

ommendations of ITU-T and Bellcore.

The chip set offers seven line and

system speed mode:

This chip set is designed to interconnect

the high speed line interface to standard

CMOS ASICs providing low speed data

interface.

622 Mbit/s ↔ 78 Mbit/s, 8 bit

311 Mbit/s ↔ 78 Mbit/s, 4 bit

155 Mbit/s ↔ 78 Mbit/s, 2 bit

155 Mbit/s ↔ 19 Mbit/s, 8 bit

280 Mbit/s ↔ 70 Mbit/s, 4 bit

140 Mbit/s ↔ 70 Mbit/s, 2 bit

140 Mbit/s ↔ 17 Mbit/s, 8 bit

The low-speed interface I/O´s are

LVTTL- level, and the high-speed I/O´s

are differential LVPECL levels (The LIA

input is usable as LVPECL input).

The GD16591/592 devices are designed

for use in both electrical and optical line

interface modules. The devices support

line speeds of:

System (local) Loop-back and Line (re-

mote) Loop-back functions offer simpli-

fied manufacturing and field testing.

Four phase selectable clock to data

timing at parallel interface.

140/155 Mbit/s NRZ mode for E4/

Selectable reference clock input fre-

quencies:

OC-3/STM-1 for an optical line inter-

face.

280/311 Mbit/s for E4/OC-3/STM-1 in

Low power consumption is achieved by

the 3.3 V single power supply and by

omitting all circuitry, which can easily be

implemented in the low speed system

ASIC, thus reducing the overall power

consumption.

17.408/19.44MHz, 34.816/

38.88MHz, and 69.632/77.76MHz.

Loop Back for System & Line test

CMI mode for electrical line interface,

where en-/decoding is made at the

system site.

modes.

48 pin EDQUAD TQFP packages.

Single supply: 3.1 ... 3.6 V.

622 Mbit/s NRZ mode line speed for

OC-12/STM-4 operation.

The devices are housed in 48 pin

EDQUAD TQFP plastic packages.

The on-chip VCO and PLL blocks for

clock generation eliminate the need for

an external high-speed clock signal.

GD16591 (Transmitter)

8:1 / 4:1 / 2:1 MUX.

Differential transmitted clock output.

LVPECL data outputs.

Optional forward/counter clocking

GD16591

MUX/

Retiming PLL

scheme.

Power dissipation, typ.: 350 mW

CMOS System ASIC

Data

70/78 Mbit/s

17/19 Mbit/s

Line Interface

2 / 4 / 8 bit

Clock

140/155 Mbit/s (optical)

280/311 Mbit/s (electrical)

622 Mbit/s (STM-4 opt.)

GD16592 (Receiver)

1:8 / 1:4 / 1:2 DeMUX.

Clock and Data Recovery:

Bang-Bang phase detector between

VCO clock and data.

LIA: serial differential input voltage

System / Line Loop Back

range 10 ... 1400 mV_PP.

Power dissipation, typ.: 450 mW

Data

70/78 Mbit/s

17/19 Mbit/s

Line Interface

2 / 4 / 8 bit

Clock

140/155 Mbit/s (optical)

280/311 Mbit/s (electrical)

622 Mbit/s (STM-4 opt.)

Applications

Tele Communication systems:

–

SDH/SONET

PDH

ATM over SDH/SONET

GD16592

DeMUX/

CDR with PLL

12 3 4 5 6 7...16

中文翻译

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