10 Gbit/s
Receiver, CDR and
DeMUX
GD16584/GD16588
(FEC)
an Intel company
Preliminary
General Description
Features
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GD16584 and GD16588 are Receiver
chips for use in STM-64/192 and Optical
Transport Networking (OTN) systems.
500 ppm from the reference clock, it
automatically switches the phase and fre-
quency detector into the PLL loop. In the
auto lock mode the locking range is
selectable between 500 or 2000 ppm.
Complete Clock and Data Recovery
IC with auto acquisition.
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1:16 DeMUX with differential
622 Mbit/s data outputs
The component is available in two ver-
sions:
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GD16584 for 9.5328 Gbit/s.
GD16588 for 10.66 Gbit/s for OTN or
When the VCO frequency is within the
lock range, the Bang-Bang Phase Detec-
tor takes over. It controls the phase of
the VCO until the sampling point of data
is in the middle of the bit period, where
the eye opening is largest. A ±40 mV
Decision Threshold Control (DTC) is pro-
vided at the 10 Gbit/s input.
622 MHz Clock output.
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Forward Error Correction (FEC).
Except the different operating bit rates
the two versions are functional identical.
LVDS compatible clock and data
outputs.
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OIF99.102.5 compliant timing.
The receiver is a Clock and Data Reco-
very IC with:
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155 or 622 MHz Reference Clock.
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a low noise VCO
a Bang-Bang Phase Detector
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The 10 Gbit/s input data is sampled and
de-multiplexed by the 1:16 DeMUX. The
parallel output interface is synchronised
with the 622 MHz output clock. The clock
and data outputs are LVDS compatible.
Input Decision Threshold Control
(DTC): ±40 mV.
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a 1:16 De-multiplexer
a Lock Detect
a Phase and Frequency Detector.
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Low noise VCO with 5 % tuning
range.
Clock and data are regenerated by using
a Phase Locked Loop (PLL) with an ex-
ternal passive loop filter.
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The device operates from a dual -5.2 V
and +3.3 V power supply. The power dis-
sipation is 3.3 W, typical.
Dual supply operation: -5.2 V and
+3.3 V.
The VCO frequency is controlled by one
of the two Phase Detectors in order to
ensure capture and lock to the line data
rate. The Lock Detector circuit monitors
the VCO frequency and determines when
the VCO is within the lock range. When
the frequency deviates more than
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Power dissipation: 3.3 W (typ).
The device is manufactured in a Silicon
Bipolar process and packaged in an 132
balls 13 × 13 mm Ceramic Ball Grid
Array (CBGA).
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Silicon Bipolar technology.
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132 balls Ceramic BGA 13 × 13 mm
package.
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VCO
CKOUT
CKOUTN
Available in two versions:
Timing Control
VCTL
–
–
GD16584 for 10 Gbit/s
GD16588 for 10.66 Gbit/s
DO0
DON0
Parallel
Output
Data
1:16
DI
DIN
Bang
Bang
Applications
Demultiplexer
Phase
Detector
DO15
DON15
Decision
Threshold
Control
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DTC
Telecommunication systems:
DTCN
–
–
–
SDH STM-64
U
D
SONET OC-192.
Optical Transport Networking
(OTN)
PCTL
Phase
Frequency
Detector
–
FEC applications
(PHIGH)
(PLOW)
REFCK
REFCKN
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Fibre optic test equipment.
Submarine systems.
1/4
Lock
Detect
LOCK
RESET TCK
SEL3
SEL1
SEL2
VCC
VDD
VDDA VDDO
VEE
VEEA
Data Sheet Rev.: 10