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GD16585-EF PDF预览

GD16585-EF

更新时间: 2024-09-24 20:08:03
品牌 Logo 应用领域
英特尔 - INTEL /
页数 文件大小 规格书
17页 183K
描述
Mux/Demux, 1-Func, Bipolar, CBGA132, 13 X 13 MM, CERAMIC, BGA-132

GD16585-EF 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:BGA,针数:132
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.84应用程序:SONET;SDH
JESD-30 代码:S-CBGA-B132长度:13 mm
负电源额定电压:-5.2 V功能数量:1
端子数量:132最高工作温度:70 °C
最低工作温度:封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY认证状态:Not Qualified
座面最大高度:2.1 mm表面贴装:YES
技术:BIPOLAR电信集成电路类型:ATM/SONET/SDH MUX/DEMUX
温度等级:COMMERCIAL端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
宽度:13 mmBase Number Matches:1

GD16585-EF 数据手册

 浏览型号GD16585-EF的Datasheet PDF文件第2页浏览型号GD16585-EF的Datasheet PDF文件第3页浏览型号GD16585-EF的Datasheet PDF文件第4页浏览型号GD16585-EF的Datasheet PDF文件第5页浏览型号GD16585-EF的Datasheet PDF文件第6页浏览型号GD16585-EF的Datasheet PDF文件第7页 
10 Gbit/s  
Transmitter MUX  
with Re-timing  
GD16585/GD16589  
(FEC)  
an Intel company  
Preliminary  
General Description  
Features  
l
GD16585 and GD16589 are transmitter  
chips used in SDH STM-64 and SONET  
OC-192 optical communication systems.  
data stream is re-timed by the high-  
speed clock from the VCO.  
PLL based CMU with on-chip 10 GHz  
or 10.66 GHz VCO.  
l
The parallel input interface features  
GIGA’s unique self-synchronizing dy-  
namic phase alignment scheme that al-  
lows both:  
16:1 Multiplexer with a last stage  
re-timing.  
The device is available in two versions:  
u
GD16585 for 9.5328 Gbit/s.  
GD16589 for 10.66 Gbit/s with  
l
u
OIF99.102.5 compliant timing .  
u
Forward Error Correction (FEC).  
Except the different operating bit rate the  
two versions are functional identical.  
Source synchronous counter clocking  
for OIF99.102.5 interfaces.  
Forward clocking with phase nulling  
l
LVDS compatible parallel data and  
clock inputs  
u
and jitter clean-up of the clock.  
These schemes enable the serializer to  
absorb output delay variations from the  
upstream System ASIC without use of  
initialization or reset.  
l
The transmitter integrates the main func-  
tions of the serializer which are:  
CML compatible serial data output.  
l
u
Clock Multiply Unit (CMU)  
16:1 Multiplexer in a single monolithic  
IC.  
155 MHz or 622 MHz reference clock  
input (selectable).  
u
l
The data and clock inputs to the MUX  
are LVDS and the output data is CML  
compatible.  
Divide by 16 clock output.  
The CMU consists of Phase Locked  
Loop (PLL) controlled from an external  
reference clock. The PLL characteristics  
are controlled by an external loop filter al-  
lowing the user to optimize the jitter  
perfomance of the device.  
l
PLL out of lock detector.  
l
The device operates from a dual -5.2 V  
and +3.3 V power supply. The power dis-  
sipation is 2.2 W, typical.  
Dual supply operation: -5.2 V and  
+3.3 V  
l
Low power dissipation: 2.2 W (typ.).  
The 16:1 Multiplexer accepts 16 parallel  
input bits at 622.88 Mbit/s (or 666 Mbit/s)  
that are serialized into a 9.9538 Gbit/s (or  
10.66 Gbit/s) data stream. The serialized  
The device is manufactured in a Silicon  
Bipolar process and packaged in an 132  
balls 13 × 13 mm Ceramic/Plastic Ball  
Grid Array (CBGA).  
l
Available in three package versions:  
EB: 132 ball (16 mill) Ceramic  
BGA 13 × 13 mm  
EF: 132 ball (20 mill) Ceramic  
BGA 13 × 13 mm  
FB: 132 ball (20 mill) Plastic  
BGA 13 × 13 mm  
DI0  
DIN0  
l
l
VCUR  
FF  
16:1  
OUT  
OUTN  
Parallel  
Input Data  
Available in two versions:  
Multiplexer  
GD16585 for 10 Gbit/s  
GD16589 for 10.66 Gbit/s  
DI15  
DIN15  
VCO  
VCTL  
Timing  
Control  
SEL1  
SEL2  
Phase  
Applications  
Selector  
Phase  
CKOUT  
CKOUTN  
PCTL  
Frequency  
Detector  
l
Telecommunication systems:  
(PHIGH)  
(PLOW)  
SDH STM-64  
CKI  
CKIN  
PFCX  
SONET OC-192  
Optical Transport Networking  
(OTN)  
NLDET  
FEC applications  
TCK  
l
Fibre optic test equipment.  
PCTLX  
SGNX  
SEL3  
REFCK/N VCC VDD VDDO VDDA VEE  
Data Sheet Rev.: 13  

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