Datasheet > GAL20VP8

GAL20VP8

更新时间： 2024-11-07 22:08:31

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
17页	262K
描述
High-Speed E2CMOS PLD Generic Array Logic

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中文翻译

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GAL20VP8 数据手册

GAL20VP8

High-Speed E²CMOS PLD

Generic Array Logic™

Features

Functional Block Diagram

• HIGH DRIVE E²CMOS^®GAL^®DEVICE

— TTL Compatible 64 mA Output Drive

— 15 ns Maximum Propagation Delay

— Fmax = 80 MHz

I/CLK

IMUX

CLK

— 10 ns Maximum from Clock Input to Data Output

I/O/Q

— UltraMOS^®Advanced CMOS Technology

OLMC

• ENHANCED INPUT AND OUTPUT FEATURES

— Schmitt Trigger Inputs

— Programmable Open-Drain or Totem-Pole Outputs

— Active Pull-Ups on All Inputs and I/O pins

• E²CELL TECHNOLOGY

— Reconfigurable Logic

OLMC

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

• EIGHT OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

— Architecturally Compatible with Standard GAL20V8

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

— 100% Functional Testability

• APPLICATIONS INCLUDE:

— Ideal for Bus Control & Bus Arbitration Logic

— Bus Address Decode Logic

— Memory Address, Data and Control Circuits

— DMA Control

OLMC

IMUX

I/OE

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

Description

Pin Configuration

The GAL20VP8, with 64 mA drive capability and 15 ns maximum

propagation delay time is ideal for Bus and Memory control appli-

PLCC

DIP

cations.

The GAL20VP8 is manufactured using Lattice

Semiconductor's advanced E²CMOS process which combines

CMOS with Electrically Erasable (E²) floating gate technology. High

speed erase times (<100ms) allow the devices to be reprogrammed

quickly and efficiently.

I/CLK

I/O/Q

GND

GAL

System bus and memory interfaces require control logic before

driving the bus or memory interface signals. The GAL20VP8

combines the familiar GAL20V8 architecture with bus drivers as

its outputs. The generic architecture provides maximum design flex-

ibility by allowing the Output Logic Macrocell (OLMC) to be con-

figured by the user. The 64mAoutput drive eliminates the need for

additional devices to provide bus-driving capability.

I/O/Q

20VP8

Vcc

23 I/O/Q

GAL20VP8

Top View

Vcc

GND

I/O/Q

Unique test circuitry and reprogrammable cells allow completeAC,

DC, and functional testing during manufacture. As a result,

Lattice Semiconductor delivers 100% field programmability and

functionality of all GAL products. In addition, 100 erase/write cycles

and data retention in excess of 20 years are specified.

I/O/Q

I/OE

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

December 1997

20vp8_03

12 3 4 5 6 7...17

中文翻译

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与GAL20VP8相关器件

型号	品牌	获取价格	描述	数据表
GAL20VP8B-15LJ	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic
GAL20VP8B-15LP	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic
GAL20VP8B-25LJ	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic
GAL20VP8B-25LP	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic
GAL20XV10	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic
GAL20XV10B-10LJ	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic
GAL20XV10B-10LP	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic
GAL20XV10B-15LJ	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic
GAL20XV10B-15LJI	LATTICE	获取价格	EE PLD, 15ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28
GAL20XV10B-15LP	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic

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