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GAL22LV10C-10LJN PDF预览

GAL22LV10C-10LJN

更新时间: 2024-09-21 13:07:55
品牌 Logo 应用领域
莱迪思 - LATTICE /
页数 文件大小 规格书
18页 218K
描述
EE PLD, 10ns, PAL-Type, CMOS, PQCC28, LEAD FREE, PLASTIC, LCC-28

GAL22LV10C-10LJN 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QLCC包装说明:LEAD FREE, PLASTIC, LCC-28
针数:28Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.7架构:PAL-TYPE
最大时钟频率:71 MHzJESD-30 代码:S-PQCC-J28
JESD-609代码:e3长度:11.5062 mm
湿度敏感等级:1专用输入次数:11
I/O 线路数量:10输入次数:22
输出次数:10产品条款数:132
端子数量:28最高工作温度:75 °C
最低工作温度:组织:11 DEDICATED INPUTS, 10 I/O
输出函数:MACROCELL封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC28,.5SQ
封装形状:SQUARE封装形式:CHIP CARRIER
峰值回流温度(摄氏度):245电源:3.3 V
可编程逻辑类型:EE PLD传播延迟:10 ns
认证状态:Not Qualified座面最大高度:4.572 mm
子类别:Programmable Logic Devices最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL EXTENDED端子面层:Matte Tin (Sn)
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:40
宽度:11.5062 mmBase Number Matches:1

GAL22LV10C-10LJN 数据手册

 浏览型号GAL22LV10C-10LJN的Datasheet PDF文件第2页浏览型号GAL22LV10C-10LJN的Datasheet PDF文件第3页浏览型号GAL22LV10C-10LJN的Datasheet PDF文件第4页浏览型号GAL22LV10C-10LJN的Datasheet PDF文件第5页浏览型号GAL22LV10C-10LJN的Datasheet PDF文件第6页浏览型号GAL22LV10C-10LJN的Datasheet PDF文件第7页 
GAL22LV10  
Low Voltage E2CMOS PLD  
Generic Array Logic™  
FUNCTIONAL BLOCK DIAGRAM  
FEATURES  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— 4 ns Maximum Propagation Delay  
— Fmax = 250 MHz  
RESET  
I/CLK  
8
— 3 ns Maximum from Clock Input to Data Output  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
I/O/Q  
I/O/Q  
— UltraMOS® Advanced CMOS Technology  
I
I
I
I
I
I
• 3.3V LOW VOLTAGE 22V10 ARCHITECTURE  
— JEDEC-Compatible 3.3V Interface Standard  
— 5V Compatible Inputs  
— I/O Interfaces with Standard 5V TTL Devices  
(GAL22LV10C)  
10  
12  
I/O/Q  
I/O/Q  
• ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D)  
• E2 CELL TECHNOLOGY  
— Reconfigurable Logic  
— Reprogrammable Cells  
— 100% Tested/100% Yields  
— High Speed Electrical Erasure (<100ms)  
— 20 Year Data Retention  
14  
16  
16  
14  
I/O/Q  
I/O/Q  
• TEN OUTPUT LOGIC MACROCELLS  
— Maximum Flexibility for Complex Logic Designs  
— Programmable Output Polarity  
I
I
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS  
— 100% Functional Testability  
12  
10  
• APPLICATIONS INCLUDE:  
— Glue Logic for 3.3V Systems  
— DMA Control  
— State Machine Control  
— High Speed Graphics Processing  
I
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— Standard Logic Speed Upgrade  
8
• ELECTRONIC SIGNATURE FOR IDENTIFICATION  
DESCRIPTION  
I
PRESET  
The GAL22LV10D, at 4 ns maximum propagation delay time,  
provides the highest speed performance available in the PLD  
market. The GAL22LV10C can interface with both 3.3V and 5V  
signal levels. The GAL22LV10 is manufactured using Lattice  
Semiconductor's advanced 3.3V E2CMOS process, which com-  
bines CMOS with Electrically Erasable (E2) floating gate technol-  
ogy. High speed erase times (<100ms) allow the devices to be  
reprogrammed quickly and efficiently.  
PIN CONFIGURATION  
PLCC  
4
2
28  
26  
5
I
25  
I/O/Q  
I/O/Q  
I/O/Q  
The generic architecture provides maximum design flexibility by  
allowing the Output Logic Macrocell (OLMC) to be configured by  
the user.  
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7
9
23  
21  
19  
GAL22LV10  
Top View  
NC  
NC  
Unique test circuitry and reprogrammable cells allow complete  
AC, DC, and functional testing during manufacture. As a result,  
Lattice Semiconductor delivers 100% field programmability and  
functionality of all GAL products. In addition, 100 erase/write  
cycles and data retention in excess of 20 years are specified.  
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I/O/Q  
I/O/Q  
I/O/Q  
11  
12  
14  
16  
18  
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com  
July 1997  
22lv10_03  
1

GAL22LV10C-10LJN 替代型号

型号 品牌 替代类型 描述 数据表
GAL22LV10C-10LJ LATTICE

完全替代

Low Voltage E2CMOS PLD Generic Array Logic⑩
PALLV22V10-10JC LATTICE

完全替代

Low-Voltage Zero Power 24-Pin EE CMOS Versatile PAL Device

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