Datasheet > GAL20XV10

GAL20XV10

更新时间： 2024-09-20 22:08:35

品牌	Logo	应用领域
莱迪思 - LATTICE		/
页数	文件大小	规格书
14页	235K
描述
High-Speed E2CMOS PLD Generic Array Logic

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GAL20XV10 数据手册

GAL20XV10

High-Speed E²CMOS PLD

Generic Array Logic™

Features

Functional Block Diagram

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— 10 ns Maximum Propagation Delay

— Fmax = 100 MHz

I/CLK

— 7 ns Maximum from Clock Input to Data Output

— TTL Compatible 16 mA Outputs

OLMC

I/O/Q

— UltraMOS^®Advanced CMOS Technology

• 50% to 75% REDUCTION IN POWER FROM BIPOLAR

— 90mA Maximum Icc

— 75mA Typical Icc

I/O/Q

• ACTIVE PULL-UPS ON ALL PINS

• E²CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100 ms)

— 20 Year Data Retention

I/O/Q

• TEN OUTPUT LOGIC MACROCELLS

— XOR Gate Capability on all Outputs

— Full Function and Parametric Compatibility with

PAL12L10, 20L10, 20X10, 20X8, 20X4

— Registered or Combinatorial with Polarity

I/O/Q

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

• APPLICATIONS INCLUDE:

— High Speed Counters

— Graphics Processing

— Comparators

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

Description

I/OE

The GAL20XV10 combines a high performance CMOS process

with electrically erasable (E²) floating gate technology to provide

the highest speed Exclusive-OR PLD available in the market. At

90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides

a substantial savings in power when compared to bipolar counter-

parts. E²CMOS technology offers high speed (<100ms) erase

times providing the ability to reprogram, reconfigure or test the de-

vices quickly and efficiently.

Pin Configuration

DIP

PLCC

Vcc

I/CLK

I/O/Q

GAL

20XV10

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user. An important subset of the many architecture configu-

rations possible with the GAL20XV10 are the PAL^®architectures

listed in the macrocell description section of this document. The

GAL20XV10 is capable of emulating these PAL architectures with

full function and parametric compatibility.

25 I/O/Q

I/O/Q

23 I/O/Q

GAL20XV10

Top View

I/O/Q

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacturing. As a result, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

13 I/OE

GND

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com

July 1997

20xv10_02

12 3 4 5 6 7...14

中文翻译

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与GAL20XV10相关器件

型号	品牌	获取价格	描述	数据表
GAL20XV10B-10LJ	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic
GAL20XV10B-10LP	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic
GAL20XV10B-15LJ	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic
GAL20XV10B-15LJI	LATTICE	获取价格	EE PLD, 15ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28
GAL20XV10B-15LP	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic
GAL20XV10B-15LPI	LATTICE	获取价格	EE PLD, 15ns, PAL-Type, CMOS, PDIP24, PLASTIC, DIP-24
GAL20XV10B-20LJ	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic
GAL20XV10B-20LJI	LATTICE	获取价格	EE PLD, 20ns, PAL-Type, CMOS, PQCC28, PLASTIC, LCC-28
GAL20XV10B-20LP	LATTICE	获取价格	High-Speed E2CMOS PLD Generic Array Logic
GAL20XV10B-20LPI	LATTICE	获取价格	EE PLD, 20ns, PAL-Type, CMOS, PDIP24, PLASTIC, DIP-24

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