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GAL20XV10B-20LP PDF预览

GAL20XV10B-20LP

更新时间： 2024-11-09 22:08:35
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑器件光电二极管输入元件时钟
页数 文件大小 规格书
14页 235K
描述
High-Speed E2CMOS PLD Generic Array Logic

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中文翻译

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GAL20XV10B-20LP 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：DIP包装说明：PLASTIC, DIP-24
针数：24Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.75Is Samacsys：N
其他特性：REGISTER PRELOAD; POWER-UP RESET架构：PAL-TYPE
最大时钟频率：50 MHzJESD-30 代码：R-PDIP-T24
JESD-609代码：e0长度：31.855 mm
专用输入次数：10I/O 线路数量：10
输入次数：20输出次数：10
产品条款数：40端子数量：24
最高工作温度：75 °C最低工作温度：
组织：10 DEDICATED INPUTS, 10 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP24,.3封装形状：RECTANGULAR
封装形式：IN-LINE电源：5 V
可编程逻辑类型：EE PLD传播延迟：20 ns
认证状态：Not Qualified座面最大高度：4.57 mm
子类别：Programmable Logic Devices最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL EXTENDED端子面层：Tin/Lead (Sn85Pb15)
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

GAL20XV10B-20LP 数据手册

 浏览型号GAL20XV10B-20LP的Datasheet PDF文件第2页浏览型号GAL20XV10B-20LP的Datasheet PDF文件第3页浏览型号GAL20XV10B-20LP的Datasheet PDF文件第4页浏览型号GAL20XV10B-20LP的Datasheet PDF文件第5页浏览型号GAL20XV10B-20LP的Datasheet PDF文件第6页浏览型号GAL20XV10B-20LP的Datasheet PDF文件第7页 
GAL20XV10  
High-Speed E2CMOS PLD  
Generic Array Logic™  
Features  
Functional Block Diagram  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— 10 ns Maximum Propagation Delay  
— Fmax = 100 MHz  
I/CLK  
— 7 ns Maximum from Clock Input to Data Output  
— TTL Compatible 16 mA Outputs  
4
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
I/O/Q  
I/O/Q  
— UltraMOS® Advanced CMOS Technology  
I
4
4
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR  
— 90mA Maximum Icc  
I
— 75mA Typical Icc  
I/O/Q  
I/O/Q  
I
I
I
I
I
I
• ACTIVE PULL-UPS ON ALL PINS  
• E2 CELL TECHNOLOGY  
4
4
4
4
— Reconfigurable Logic  
— Reprogrammable Cells  
— 100% Tested/100% Yields  
— High Speed Electrical Erasure (<100 ms)  
— 20 Year Data Retention  
I/O/Q  
I/O/Q  
• TEN OUTPUT LOGIC MACROCELLS  
— XOR Gate Capability on all Outputs  
— Full Function and Parametric Compatibility with  
PAL12L10, 20L10, 20X10, 20X8, 20X4  
— Registered or Combinatorial with Polarity  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
4
4
4
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS  
• APPLICATIONS INCLUDE:  
— High Speed Counters  
— Graphics Processing  
— Comparators  
I
I
• ELECTRONIC SIGNATURE FOR IDENTIFICATION  
Description  
I/OE  
The GAL20XV10 combines a high performance CMOS process  
with electrically erasable (E2) floating gate technology to provide  
the highest speed Exclusive-OR PLD available in the market. At  
90mA maximum Icc (75mA typical Icc), the GAL20XV10 provides  
a substantial savings in power when compared to bipolar counter-  
parts. E2CMOS technology offers high speed (<100ms) erase  
times providing the ability to reprogram, reconfigure or test the de-  
vices quickly and efficiently.  
Pin Configuration  
DIP  
PLCC  
1
Vcc  
24  
I/CLK  
I/O/Q  
I
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I
I
I
I
4
2
28  
26  
GAL  
20XV10  
The generic architecture provides maximum design flexibility by  
allowing the Output Logic Macrocell (OLMC) to be configured by  
the user. An important subset of the many architecture configu-  
rations possible with the GAL20XV10 are the PAL® architectures  
listed in the macrocell description section of this document. The  
GAL20XV10 is capable of emulating these PAL architectures with  
full function and parametric compatibility.  
5
7
9
I
I
I
25 I/O/Q  
I/O/Q  
23 I/O/Q  
6
GAL20XV10  
Top View  
NC  
NC  
18  
I
I
I
I
I
I/O/Q  
I/O/Q  
I/O/Q  
21  
19  
11  
14  
16  
18  
12  
I
I
I
Unique test circuitry and reprogrammable cells allow complete AC,  
DC, and functional testing during manufacturing. As a result, Lattice  
Semiconductor delivers 100% field programmability and function-  
ality of all GAL products. In addition, 100 erase/write cycles and  
data retention in excess of 20 years are specified.  
12  
13 I/OE  
GND  
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com  
July 1997  
1
20xv10_02  
1234567...14

中文翻译

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