Datasheet > GAL22LV10C-15J

GAL22LV10C-15J

更新时间： 2024-11-07 23:53:35

品牌	Logo	应用领域
其他 - ETC		/
页数	文件大小	规格书
18页	295K
描述
IC-SM-CMOS PLD

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

GAL22LV10C-15J 数据手册

GAL22LV10

Low Voltage E²CMOS PLD

Generic Array Logic™

Features

Functional Block Diagram

• HIGH PERFORMANCE E²CMOS^®TECHNOLOGY

— 4 ns Maximum Propagation Delay

— Fmax = 250 MHz

RESET

I/CLK

— 3 ns Maximum from Clock Input to Data Output

OLMC

I/O/Q

— UltraMOS^®Advanced CMOS Technology

• 3.3V LOW VOLTAGE 22V10 ARCHITECTURE

— JEDEC-Compatible 3.3V Interface Standard

— 5V Compatible Inputs

— I/O Interfaces with Standard 5V TTL Devices

(GAL22LV10C)

I/O/Q

• ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D)

• E²CELL TECHNOLOGY

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

I/O/Q

• TEN OUTPUT LOGIC MACROCELLS

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

I/O/Q

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

— 100% Functional Testability

• APPLICATIONS INCLUDE:

— Glue Logic for 3.3V Systems

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

PRESET

Description

Pin Configuration

PLCC

The GAL22LV10D, at 4 ns maximum propagation delay time, pro-

vides the highest speed performance available in the PLD market.

The GAL22LV10C can interface with both 3.3V and 5V signal levels.

The GAL22LV10 is manufactured using Lattice Semiconductor's

advanced 3.3V E²CMOS process, which combines CMOS with

Electrically Erasable (E²) floating gate technology. High speed erase

times (<100ms) allow the devices to be reprogrammed quickly and

efficiently.

I/O/Q

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user.

GAL22LV10

Top View

I/O/Q

Unique test circuitry and reprogrammable cells allow completeAC,

DC, and functional testing during manufacture. As a result, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 681-0118; 1-888-ISP-PLDS; FAX (503) 681-3037; http://www.latticesemi.com

July 1997

22lv10_03

12 3 4 5 6 7...18

中文翻译

下载PDF

与GAL22LV10C-15J相关器件

型号	品牌	获取价格	描述	数据表
GAL22LV10C-15LJ	LATTICE	获取价格	Low Voltage E2CMOS PLD Generic Array Logic⑩
GAL22LV10C-15LJI	ETC	获取价格	Electrically-Erasable PLD
GAL22LV10C-7LJ	LATTICE	获取价格	Low Voltage E2CMOS PLD Generic Array Logic⑩
GAL22LV10D-15LJ	LATTICE	获取价格	EE PLD, 15ns, CMOS, PQCC28, PLASTIC, LCC-28
GAL22LV10D-4LJ	LATTICE	获取价格	Low Voltage E2CMOS PLD Generic Array Logic⑩
GAL22LV10D-4LJN	LATTICE	获取价格	EE PLD, 4ns, PAL-Type, CMOS, PQCC28, LEAD FREE, PLASTIC, LCC-28
GAL22LV10D-5LJ	LATTICE	获取价格	Low Voltage E2CMOS PLD Generic Array Logic⑩
GAL22LV10D-5LJN	LATTICE	获取价格	EE PLD, 5ns, PAL-Type, CMOS, PQCC28, LEAD FREE, PLASTIC, LCC-28
GAL22LV10D-7LJ	LATTICE	获取价格	EE PLD, 7.5ns, CMOS, PQCC28, PLASTIC, LCC-28
GAL22LV10Z-15QJ	ETC	获取价格	Electrically-Erasable PLD

与GAL22LV10C-15J相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

21
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

20
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

44
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

38

产品中心

服务支持

精选活动

关于我们

帮助中心

GAL22LV10C-15J

GAL22LV10C-15J 数据手册

与GAL22LV10C-15J相关器件

与GAL22LV10C-15J相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

GAL22LV10C-15J

GAL22LV10C-15J 数据手册

与GAL22LV10C-15J相关器件

与GAL22LV10C-15J相关文章

您还可以找

您在本页遇到什么问题？