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GAL22LV10D-7LJ PDF预览

GAL22LV10D-7LJ

更新时间： 2024-09-21 20:34:11
品牌 Logo 应用领域
莱迪思 - LATTICE 时钟输入元件可编程逻辑
页数 文件大小 规格书
18页 210K
描述
EE PLD, 7.5ns, CMOS, PQCC28, PLASTIC, LCC-28

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GAL22LV10D-7LJ 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QLCC
包装说明：PLASTIC, LCC-28针数：28
Reach Compliance Code：not_compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.79
最大时钟频率：91 MHzJESD-30 代码：S-PQCC-J28
JESD-609代码：e0长度：11.5062 mm
湿度敏感等级：1专用输入次数：11
I/O 线路数量：10端子数量：28
最高工作温度：75 °C最低工作温度：
组织：11 DEDICATED INPUTS, 10 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装形状：SQUARE封装形式：CHIP CARRIER
峰值回流温度（摄氏度）：225可编程逻辑类型：EE PLD
传播延迟：7.5 ns认证状态：Not Qualified
座面最大高度：4.572 mm最大供电电压：3.6 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL EXTENDED端子面层：TIN LEAD
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：11.5062 mmBase Number Matches：1

GAL22LV10D-7LJ 数据手册

 浏览型号GAL22LV10D-7LJ的Datasheet PDF文件第2页浏览型号GAL22LV10D-7LJ的Datasheet PDF文件第3页浏览型号GAL22LV10D-7LJ的Datasheet PDF文件第4页浏览型号GAL22LV10D-7LJ的Datasheet PDF文件第5页浏览型号GAL22LV10D-7LJ的Datasheet PDF文件第6页浏览型号GAL22LV10D-7LJ的Datasheet PDF文件第7页 
GAL22LV10  
Low Voltage E2CMOS PLD  
Generic Array Logic™  
Features  
Functional Block Diagram  
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY  
— 4 ns Maximum Propagation Delay  
— Fmax = 250 MHz  
RESET  
I/CLK  
8
— 3 ns Maximum from Clock Input to Data Output  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
I/O/Q  
I/O/Q  
— UltraMOS® Advanced CMOS Technology  
I
I
I
I
I
I
• 3.3V LOW VOLTAGE 22V10 ARCHITECTURE  
— JEDEC-Compatible 3.3V Interface Standard  
— 5V Compatible Inputs  
— I/O Interfaces with Standard 5V TTL Devices  
(GAL22LV10C)  
10  
12  
I/O/Q  
I/O/Q  
• ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D)  
• E2 CELL TECHNOLOGY  
— Reconfigurable Logic  
— Reprogrammable Cells  
— 100% Tested/100% Yields  
— High Speed Electrical Erasure (<100ms)  
— 20 Year Data Retention  
14  
16  
16  
14  
I/O/Q  
I/O/Q  
• TEN OUTPUT LOGIC MACROCELLS  
— Maximum Flexibility for Complex Logic Designs  
— Programmable Output Polarity  
I
I
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS  
— 100% Functional Testability  
12  
10  
• APPLICATIONS INCLUDE:  
— Glue Logic for 3.3V Systems  
— DMA Control  
— State Machine Control  
— High Speed Graphics Processing  
— Standard Logic Speed Upgrade  
I
I
I
8
• ELECTRONIC SIGNATURE FOR IDENTIFICATION  
PRESET  
Description  
Pin Configuration  
PLCC  
The GAL22LV10D, at 4 ns maximum propagation delay time, pro-  
vides the highest speed performance available in the PLD market.  
The GAL22LV10C can interface with both 3.3V and 5V signal levels.  
The GAL22LV10 is manufactured using Lattice Semiconductor's  
advanced 3.3V E2CMOS process, which combines CMOS with  
Electrically Erasable (E2) floating gate technology. High speed erase  
times (<100ms) allow the devices to be reprogrammed quickly and  
efficiently.  
4
2
28  
26  
5
I
25  
I/O/Q  
I/O/Q  
I/O/Q  
I
I
7
9
23  
21  
19  
The generic architecture provides maximum design flexibility by  
allowing the Output Logic Macrocell (OLMC) to be configured by  
the user.  
GAL22LV10  
Top View  
NC  
NC  
I
I
I
I/O/Q  
I/O/Q  
I/O/Q  
Unique test circuitry and reprogrammable cells allow completeAC,  
DC, and functional testing during manufacture. As a result, Lattice  
Semiconductor delivers 100% field programmability and function-  
ality of all GAL products. In addition, 100 erase/write cycles and  
data retention in excess of 20 years are specified.  
11  
12  
14  
16  
18  
Copyright © 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
November 2000  
22lv10_04  
1
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