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GAL20VP8B-25LP PDF预览

GAL20VP8B-25LP

更新时间： 2024-09-20 22:08:31
品牌 Logo 应用领域
莱迪思 - LATTICE 可编程逻辑光电二极管输入元件时钟
页数 文件大小 规格书
17页 262K
描述
High-Speed E2CMOS PLD Generic Array Logic

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中文翻译

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GAL20VP8B-25LP 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：DIP包装说明：PLASTIC, DIP-24
针数：24Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.8Is Samacsys：N
其他特性：REGISTER PRELOAD; POWER-UP RESET架构：PAL-TYPE
最大时钟频率：40 MHzJESD-30 代码：R-PDIP-T24
JESD-609代码：e0长度：31.855 mm
专用输入次数：12I/O 线路数量：8
输入次数：20输出次数：8
产品条款数：64端子数量：24
最高工作温度：75 °C最低工作温度：
组织：12 DEDICATED INPUTS, 8 I/O输出函数：MACROCELL
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP24,.3封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：225
电源：5 V可编程逻辑类型：EE PLD
传播延迟：25 ns认证状态：Not Qualified
座面最大高度：4.57 mm子类别：Programmable Logic Devices
最大供电电压：5.25 V最小供电电压：4.75 V
标称供电电压：5 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL EXTENDED
端子面层：Tin/Lead (Sn85Pb15)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：7.62 mm
Base Number Matches：1

GAL20VP8B-25LP 数据手册

 浏览型号GAL20VP8B-25LP的Datasheet PDF文件第2页浏览型号GAL20VP8B-25LP的Datasheet PDF文件第3页浏览型号GAL20VP8B-25LP的Datasheet PDF文件第4页浏览型号GAL20VP8B-25LP的Datasheet PDF文件第5页浏览型号GAL20VP8B-25LP的Datasheet PDF文件第6页浏览型号GAL20VP8B-25LP的Datasheet PDF文件第7页 
GAL20VP8  
High-Speed E2CMOS PLD  
Generic Array Logic™  
Features  
Functional Block Diagram  
• HIGH DRIVE E2CMOS® GAL® DEVICE  
— TTL Compatible 64 mA Output Drive  
— 15 ns Maximum Propagation Delay  
— Fmax = 80 MHz  
I/CLK  
I
I
IMUX  
CLK  
— 10 ns Maximum from Clock Input to Data Output  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
— UltraMOS® Advanced CMOS Technology  
8
8
OLMC  
I
• ENHANCED INPUT AND OUTPUT FEATURES  
— Schmitt Trigger Inputs  
— Programmable Open-Drain or Totem-Pole Outputs  
— Active Pull-Ups on All Inputs and I/O pins  
• E2 CELL TECHNOLOGY  
— Reconfigurable Logic  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
OLMC  
I
8
8
8
I
I
I
I
I
— Reprogrammable Cells  
— 100% Tested/100% Yields  
— High Speed Electrical Erasure (<100ms)  
— 20 Year Data Retention  
• EIGHT OUTPUT LOGIC MACROCELLS  
— Maximum Flexibility for Complex Logic Designs  
— Programmable Output Polarity  
8
8
8
— Architecturally Compatible with Standard GAL20V8  
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS  
— 100% Functional Testability  
• APPLICATIONS INCLUDE:  
— Ideal for Bus Control & Bus Arbitration Logic  
— Bus Address Decode Logic  
— Memory Address, Data and Control Circuits  
— DMA Control  
OLMC  
IMUX  
I
I
OE  
I
I/OE  
• ELECTRONIC SIGNATURE FOR IDENTIFICATION  
Description  
Pin Configuration  
The GAL20VP8, with 64 mA drive capability and 15 ns maximum  
propagation delay time is ideal for Bus and Memory control appli-  
PLCC  
DIP  
cations.  
The GAL20VP8 is manufactured using Lattice  
Semiconductor's advanced E2CMOS process which combines  
CMOS with Electrically Erasable (E2) floating gate technology. High  
speed erase times (<100ms) allow the devices to be reprogrammed  
quickly and efficiently.  
1
I
I
24  
I/CLK  
I
I/O/Q  
I/O/Q  
I/O/Q  
I/O/Q  
GND  
I
4
2
28  
26  
GAL  
System bus and memory interfaces require control logic before  
driving the bus or memory interface signals. The GAL20VP8  
combines the familiar GAL20V8 architecture with bus drivers as  
its outputs. The generic architecture provides maximum design flex-  
ibility by allowing the Output Logic Macrocell (OLMC) to be con-  
figured by the user. The 64mAoutput drive eliminates the need for  
additional devices to provide bus-driving capability.  
5
7
25  
I
I/O/Q  
I/O/Q  
I
I
I
20VP8  
Vcc  
23 I/O/Q  
NC  
GAL20VP8  
Top View  
Vcc  
6
NC  
18  
I
I
I
9
21  
GND  
I/O/Q  
I/O/Q  
I
I
I/O/Q  
I/O/Q  
I/O/Q  
11  
19  
18  
12  
14  
16  
I
Unique test circuitry and reprogrammable cells allow completeAC,  
DC, and functional testing during manufacture. As a result,  
Lattice Semiconductor delivers 100% field programmability and  
functionality of all GAL products. In addition, 100 erase/write cycles  
and data retention in excess of 20 years are specified.  
I
I
I/O/Q  
I
12  
13  
I/OE  
Copyright © 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject  
to change without notice.  
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.  
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com  
December 1997  
20vp8_03  
1
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