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FIN1002M5X PDF预览

FIN1002M5X

更新时间: 2024-10-28 11:13:27
品牌 Logo 应用领域
安森美 - ONSEMI PC光电二极管接口集成电路
页数 文件大小 规格书
9页 226K
描述
3.3V LVDS 1 位高速差分接收器

FIN1002M5X 技术参数

是否无铅: 不含铅生命周期:Active
包装说明:LSSOP, TSOP5/6,.11,37Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:14 weeks风险等级:1.18
差分输出:NO输入特性:DIFFERENTIAL
接口集成电路类型:LINE RECEIVER接口标准:EIA-644; TIA-644
JESD-30 代码:R-PDSO-G5JESD-609代码:e3
长度:2.9 mm湿度敏感等级:1
功能数量:1端子数量:5
最高工作温度:85 °C最低工作温度:-40 °C
最大输出低电流:0.008 A封装主体材料:PLASTIC/EPOXY
封装代码:LSSOP封装等效代码:TSOP5/6,.11,37
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3 V
认证状态:Not Qualified最大接收延迟:2.5 ns
接收器位数:1座面最大高度:1.4 mm
子类别:Line Driver or Receivers最大压摆率:7 mA
最大供电电压:3.6 V最小供电电压:3 V
标称供电电压:3.3 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Tin (Sn)
端子形式:GULL WING端子节距:0.95 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:1.6 mmBase Number Matches:1

FIN1002M5X 数据手册

 浏览型号FIN1002M5X的Datasheet PDF文件第2页浏览型号FIN1002M5X的Datasheet PDF文件第3页浏览型号FIN1002M5X的Datasheet PDF文件第4页浏览型号FIN1002M5X的Datasheet PDF文件第5页浏览型号FIN1002M5X的Datasheet PDF文件第6页浏览型号FIN1002M5X的Datasheet PDF文件第7页 
DATA SHEET  
www.onsemi.com  
LVDS 1-Bit, High-Speed  
Differential Reciever  
SOT23, 5 Lead  
CASE 527AH  
FIN1002  
Description  
MARKING DIAGRAM  
This single receiver is designed for highspeed interconnects  
utilizing Low Voltage Differential Signaling (LVDS) technology. The  
receiver translates LVDS levels, with a typical differential input  
threshold of 100 mV, to LVTTL signal levels. LVDS provides low  
EMI at ultra low power dissipation even at high frequencies. This  
device is ideal for highspeed transfer of clock or data. The FIN1002  
can be paired with its companion driver, the FIN1001, or with any  
other LVDS driver.  
FN02M  
FN02  
M
= Specific Device Code  
= Date Code  
Features  
Greater than 400 Mbs Data Rate  
3.3 V Power Supply Operation  
0.4 ns Maximum Pulse Skew  
2.5 ns Maximum Propagation Delay  
Bus Pin ESD (HBM) Protection Exceeds 10 kV  
CONNECTION DIAGRAM  
R
V
OUT  
CC  
PowerOff, Overvoltage Tolerant Input and Output  
Failsafe Protection for opencircuit and Nondriven, Shorted, or  
Terminated Conditions  
GND  
R
R
IN+  
IN  
Highimpedance Output at V < 1.5 V  
CC  
(Top View)  
Meets or exceeds TIA/EIA644 LVDS Standard  
5Lead SOT23 Package Saves Space  
PIN CONFIGURATION  
PIN DEFINITIONS  
Pin No.  
Function  
Description  
1
2
3
5
4
R
OUT  
V
CC  
1
2
3
4
5
V
CC  
Power Supply  
GND  
Ground for the IC  
GND  
R
R
Noninverting Driver Input  
Inverting Driver Input  
LVTTL Data Output  
IN+  
R
R
IN−  
IN+  
IN−  
R
OUT  
ORDERING INFORMATION  
See detailed ordering and shipping information on page 7 of  
this data sheet.  
FUNCTION TABLE  
Inputs  
Outputs  
R
R
R
IN+  
IN-  
OUT  
LOW  
HIGH  
LOW  
HIGH  
HIGH  
HIGH  
LOW  
FailSafe Condition (Open, Shorted, Terminated)  
© Semiconductor Components Industries, LLC, 2016  
1
Publication Order Number:  
June, 2022 Rev 2  
FIN1002/D  

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