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FIN1002M5X_NL

更新时间: 2024-10-27 13:07:47
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
7页 1022K
描述
Line Receiver, 1 Func, 1 Rcvr, PDSO5, 1.60 MM, MO-178, SOT-23, 5 PIN

FIN1002M5X_NL 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:LSSOP, TSOP5/6,.11,37
针数:5Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.5差分输出:NO
输入特性:DIFFERENTIAL接口集成电路类型:LINE RECEIVER
接口标准:EIA-644; TIA-644JESD-30 代码:R-PDSO-G5
JESD-609代码:e3长度:2.9 mm
湿度敏感等级:1功能数量:1
端子数量:5最高工作温度:85 °C
最低工作温度:-40 °C最大输出低电流:0.008 A
封装主体材料:PLASTIC/EPOXY封装代码:LSSOP
封装等效代码:TSOP5/6,.11,37封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, LOW PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:3.3 V认证状态:Not Qualified
最大接收延迟:2.5 ns接收器位数:1
座面最大高度:1.4 mm子类别:Line Driver or Receivers
最大压摆率:7 mA最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.95 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:1.6 mm
Base Number Matches:1

FIN1002M5X_NL 数据手册

 浏览型号FIN1002M5X_NL的Datasheet PDF文件第2页浏览型号FIN1002M5X_NL的Datasheet PDF文件第3页浏览型号FIN1002M5X_NL的Datasheet PDF文件第4页浏览型号FIN1002M5X_NL的Datasheet PDF文件第5页浏览型号FIN1002M5X_NL的Datasheet PDF文件第6页浏览型号FIN1002M5X_NL的Datasheet PDF文件第7页 
February 2002  
Revised February 2002  
FIN1002  
LVDS 1-Bit High Speed Differential Receiver  
General Description  
Features  
This single receiver is designed for high speed intercon-  
nects utilizing Low Voltage Differential Signaling (LVDS)  
technology. The receiver translates LVDS levels, with a typ-  
ical differential input threshold of 100 mV, to LVTTL signal  
levels. LVDS provides low EMI at ultra low power dissipa-  
tion even at high frequencies. This device is ideal for high  
speed transfer of clock or data.  
Greater than 400Mbs data rate  
3.3V power supply operation  
0.4ns maximum pulse skew  
2.5ns maximum propagation delay  
Bus pin ESD (HBM) protection exceeds 10kV  
Power-Off over voltage tolerant input and output  
The FIN1002 can be paired with its companion driver, the  
FIN1001, or with any other LVDS driver.  
Fail safe protection for open-circuit and non-driven,  
shorted or terminated conditions  
High impedance output at VCC < 1.5V  
Meets or exceeds the TIA/EIA-644 LVDS standard  
5-Lead SOT23 package saves space  
Ordering Code:  
Order Number Package Number  
Package Description  
FIN1002M5  
MA05B  
MA05B  
5-Lead SOT23, JEDEC MO-178, 1.6mm [250 Units on Tape and Reel]  
5-Lead SOT23, JEDEC MO-178, 1.6mm [3000 Units on Tape and Reel]  
FIN1002M5X  
Pin Descriptions  
Connection Diagram  
Pin Name  
ROUT  
RIN+  
Description  
Pin Assignment for SOT package  
LVTTL Data Output  
Non-inverting Driver Input  
Inverting Driver Input  
Power Supply  
RIN−  
VCC  
GND  
NC  
Ground  
No Connect  
Top View  
Function Table  
Input  
Outputs  
RIN+  
RIN−  
ROUT  
L
H
L
L
H
H
H
Fail Safe Condition  
H = HIGH Logic Level  
L = LOW Logic Level  
Fail Safe = Open, Shorted, Terminated  
© 2002 Fairchild Semiconductor Corporation  
DS500730  
www.fairchildsemi.com  

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