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FIN1025 PDF预览

FIN1025

更新时间: 2024-10-26 22:31:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
7页 267K
描述
3.3V LVDS 2-Bit High Speed Differential Driver

FIN1025 数据手册

 浏览型号FIN1025的Datasheet PDF文件第2页浏览型号FIN1025的Datasheet PDF文件第3页浏览型号FIN1025的Datasheet PDF文件第4页浏览型号FIN1025的Datasheet PDF文件第5页浏览型号FIN1025的Datasheet PDF文件第6页浏览型号FIN1025的Datasheet PDF文件第7页 
June 2002  
Revised June 2002  
FIN1025  
3.3V LVDS 2-Bit High Speed Differential Driver  
General Description  
Features  
Greater than 400Mbs data rate  
Flow-through pinout simplifies PCB layout  
3.3V power supply operation  
This dual driver is designed for high speed interconnects  
utilizing Low Voltage Differential Signaling (LVDS) technol-  
ogy. The driver translates LVTTL signal levels to LVDS lev-  
els with a typical differential output swing of 350mV which  
provides low EMI at ultra low power dissipation even at  
high frequencies. This device is ideal for high speed trans-  
fer of clock and data.  
0.4ns maximum differential pulse skew  
1.7ns maximum propagation delay  
Low power dissipation  
The FIN1025 can be paired with its companion receiver,  
the FIN1026, or any other LVDS receiver.  
Power-Off protection  
Meets or exceeds the TIA/EIA-644 LVDS standard  
14-Lead TSSOP package saves space  
Ordering Code:  
Order Number Package Number  
Package Description  
FIN1025MTC  
MTC14  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Pin Descriptions  
Pin Name  
IN1, DIN2  
Description  
LVTTL Data Inputs  
D
,
DOUT1+, DOUT2+  
DOUT1, DOUT2−  
EN  
Non-Inverting Driver Outputs  
Inverting Driver Outputs  
Driver Enable Pin  
EN  
VCC  
GND  
NC  
Inverting Driver Enable Pin  
Power Supply  
Ground  
No Connect  
Truth Table  
Inputs  
Outputs  
DIN  
DOUT+  
DOUT−  
EN  
EN  
H
L or OPEN  
L or OPEN  
L or OPEN  
H
H
H
L
L
Z
Z
L
H
H
Z
Z
H
L
OPEN  
X
H
X
L or OPEN  
X
X
H = HIGH Logic Level  
L = LOW Logic Level  
X = Don’t Care  
Z = High Impedance  
© 2002 Fairchild Semiconductor Corporation  
DS500783  
www.fairchildsemi.com  

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