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FIN1018MX PDF预览

FIN1018MX

更新时间: 2024-10-26 22:31:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
8页 1042K
描述
3.3V LVDS 1-Bit High Speed Differential Receiver

FIN1018MX 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:2.96
输入特性:DIFFERENTIAL接口集成电路类型:LINE RECEIVER
接口标准:EIA-644; TIA-644JESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9 mm
湿度敏感等级:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C最大输出低电流:0.008 A
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
最大接收延迟:2.5 ns接收器位数:1
座面最大高度:1.75 mm子类别:Line Driver or Receivers
最大压摆率:7 mA最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

FIN1018MX 数据手册

 浏览型号FIN1018MX的Datasheet PDF文件第2页浏览型号FIN1018MX的Datasheet PDF文件第3页浏览型号FIN1018MX的Datasheet PDF文件第4页浏览型号FIN1018MX的Datasheet PDF文件第5页浏览型号FIN1018MX的Datasheet PDF文件第6页浏览型号FIN1018MX的Datasheet PDF文件第7页 
March 2001  
Revised April 2002  
FIN1018  
3.3V LVDS 1-Bit High Speed Differential Receiver  
General Description  
Features  
This single receiver is designed for high speed intercon-  
nects utilizing Low Voltage Differential Signaling (LVDS)  
technology. The receiver translates LVDS levels, with a typ-  
ical differential input threshold of 100 mV, to LVTTL signal  
levels. LVDS provides low EMI at ultra low power dissipa-  
tion even at high frequencies. This device is ideal for high  
speed transfer of clock or data.  
Greater than 400Mbs data rate  
3.3V power supply operation  
0.4ns maximum pulse skew  
2.5ns maximum propagation delay  
Low power dissipation  
Power-Off protection  
The FIN1018 can be paired with its companion driver, the  
FIN1017, or with any other LVDS driver.  
Fail safe protection for open-circuit, shorted and termi-  
nated conditions  
Meets or exceeds the TIA/EIA-644 LVDS standard  
Flow-through pinout simplifies PCB layout  
8-Lead SOIC and US-8 packages save space  
Ordering Code:  
Order Number Package Number  
Package Description  
FIN1018M  
M08A  
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
[TUBE]  
FIN1018MX  
FIN1018K8X  
M08A  
8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
[TAPE and REEL]  
MAB08A  
8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide  
[TAPE and REEL]  
Pin Descriptions  
Connection Diagrams  
Pin Name  
ROUT  
RIN+  
Description  
8-Lead SOIC  
LVTTL Data Output  
Non-inverting Driver Input  
Inverting Driver Input  
Power Supply  
RIN−  
VCC  
GND  
NC  
Ground  
No Connect  
Pin Assignment for US-8 Package  
Function Table  
Input  
Outputs  
RIN+  
RIN−  
ROUT  
L
H
L
L
H
H
H
Fail Safe Condition  
H = HIGH Logic Level  
L = LOW Logic Level  
Fail Safe = Open, Shorted, Terminated  
TOP VIEW  
© 2002 Fairchild Semiconductor Corporation  
DS500502  
www.fairchildsemi.com  

FIN1018MX 替代型号

型号 品牌 替代类型 描述 数据表
PI90LV018AWE PERICOM

完全替代

Line Receiver, 1 Func, 1 Rcvr, CMOS, PDSO8, 0.150 INCH, GREEN, SOIC-8
DS90LV018ATM/NOPB TI

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3V LVDS Single CMOS Differential Line Receiver
SN65LVDS2D TI

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