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FIN1019

更新时间: 2024-10-26 22:31:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
14页 1468K
描述
3.3V LVDS High Speed Differential Driver/Receiver

FIN1019 数据手册

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April 2001  
Revised September 2001  
FIN1019  
3.3V LVDS High Speed Differential Driver/Receiver  
General Description  
Features  
This driver and receiver pair are designed for high speed  
interconnects utilizing Low Voltage Differential Signaling  
(LVDS) technology. The driver translates LVTTL signals to  
LVDS levels with a typical differential output swing of  
350mV and the receiver translates LVDS signals, with a  
typical differential input threshold of 100mV, into LVTTL  
levels. LVDS technology provides low EMI at ultra low  
power dissipation even at high frequencies. This device is  
ideal for high speed clock or data transfer.  
Greater than 400Mbs data rate  
3.3V power supply operation  
0.5ns maximum differential pulse skew  
2.5ns maximum propagation delay  
Low power dissipation  
Power-Off protection  
100mV receiver input sensitivity  
Fail safe protection open-circuit, shorted and terminated  
conditions  
Meets or exceeds the TIA/EIA-644 LVDS standard  
Flow-through pinout simplifies PCB layout  
14-Lead SOIC and TSSOP packages save space  
Ordering Code:  
Order Number Package Number  
Package Description  
FIN1019M  
M14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
FIN1019MTC  
MTC14  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Function Table  
Connection Diagram  
Inputs  
Outputs  
ROUT  
RIN+  
RIN−  
RE  
L
L
H
X
H
L
L
H
Z
L
X
H
L
Fail Safe Condition  
H
DIN  
DE  
DOUT+  
DOUT−  
L
H
H
L
L
H
Z
L
H
L
Pin Descriptions  
H
X
Z
Pin Name  
Description  
OpenCircuit or Z  
H
H
DIN  
DOUT+  
DOUT−  
DE  
LVTTL Data Input  
H = HIGH Logic Level  
Z = High Impedance  
L = LOW Logic Level  
Fail Safe = Open, Shorted, Terminated  
X = Don’t Care  
Non-inverting LVDS Output  
Inverting LVDS Output  
Driver Enable (LVTTL, Active HIGH)  
Non-Inverting LVDS Input  
Inverting LVDS Input  
RIN+  
RIN−  
ROUT  
LVTTL Receiver Output  
RE  
VCC  
GND  
NC  
Receiver Enable (LVTTL, Active LOW)  
Power Supply  
Ground  
No Connect  
© 2001 Fairchild Semiconductor Corporation  
DS500506  
www.fairchildsemi.com  

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