Datasheet > FIN1018

FIN1018

更新时间： 2024-10-26 22:31:59

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		/
页数	文件大小	规格书
8页	1042K
描述
3.3V LVDS 1-Bit High Speed Differential Receiver

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数据手册

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FIN1018 数据手册

March 2001

Revised April 2002

FIN1018

3.3V LVDS 1-Bit High Speed Differential Receiver

General Description

Features

This single receiver is designed for high speed intercon-

nects utilizing Low Voltage Differential Signaling (LVDS)

technology. The receiver translates LVDS levels, with a typ-

ical differential input threshold of 100 mV, to LVTTL signal

levels. LVDS provides low EMI at ultra low power dissipa-

tion even at high frequencies. This device is ideal for high

speed transfer of clock or data.

■ Greater than 400Mbs data rate

■ 3.3V power supply operation

■ 0.4ns maximum pulse skew

■ 2.5ns maximum propagation delay

■ Low power dissipation

■ Power-Off protection

The FIN1018 can be paired with its companion driver, the

FIN1017, or with any other LVDS driver.

■ Fail safe protection for open-circuit, shorted and termi-

nated conditions

■ Meets or exceeds the TIA/EIA-644 LVDS standard

■ Flow-through pinout simplifies PCB layout

■ 8-Lead SOIC and US-8 packages save space

Ordering Code:

Order Number Package Number

Package Description

FIN1018M

M08A

8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

[TUBE]

FIN1018MX

FIN1018K8X

M08A

8-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

[TAPE and REEL]

MAB08A

8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide

[TAPE and REEL]

Pin Descriptions

Connection Diagrams

Pin Name

R_OUT

R_IN+

Description

8-Lead SOIC

LVTTL Data Output

Non-inverting Driver Input

Inverting Driver Input

Power Supply

R_IN−

V_CC

GND

Ground

No Connect

Pin Assignment for US-8 Package

Function Table

Input

Outputs

R_IN+

R_IN−

R_OUT

Fail Safe Condition

H = HIGH Logic Level

L = LOW Logic Level

Fail Safe = Open, Shorted, Terminated

TOP VIEW

DS500502

www.fairchildsemi.com

12 3 4 5 6 7 8

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