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FIN1002

更新时间: 2024-10-26 22:31:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD /
页数 文件大小 规格书
7页 1022K
描述
LVDS 1-Bit High Speed Differential Receiver

FIN1002 数据手册

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February 2002  
Revised February 2002  
FIN1002  
LVDS 1-Bit High Speed Differential Receiver  
General Description  
Features  
This single receiver is designed for high speed intercon-  
nects utilizing Low Voltage Differential Signaling (LVDS)  
technology. The receiver translates LVDS levels, with a typ-  
ical differential input threshold of 100 mV, to LVTTL signal  
levels. LVDS provides low EMI at ultra low power dissipa-  
tion even at high frequencies. This device is ideal for high  
speed transfer of clock or data.  
Greater than 400Mbs data rate  
3.3V power supply operation  
0.4ns maximum pulse skew  
2.5ns maximum propagation delay  
Bus pin ESD (HBM) protection exceeds 10kV  
Power-Off over voltage tolerant input and output  
The FIN1002 can be paired with its companion driver, the  
FIN1001, or with any other LVDS driver.  
Fail safe protection for open-circuit and non-driven,  
shorted or terminated conditions  
High impedance output at VCC < 1.5V  
Meets or exceeds the TIA/EIA-644 LVDS standard  
5-Lead SOT23 package saves space  
Ordering Code:  
Order Number Package Number  
Package Description  
FIN1002M5  
MA05B  
MA05B  
5-Lead SOT23, JEDEC MO-178, 1.6mm [250 Units on Tape and Reel]  
5-Lead SOT23, JEDEC MO-178, 1.6mm [3000 Units on Tape and Reel]  
FIN1002M5X  
Pin Descriptions  
Connection Diagram  
Pin Name  
ROUT  
RIN+  
Description  
Pin Assignment for SOT package  
LVTTL Data Output  
Non-inverting Driver Input  
Inverting Driver Input  
Power Supply  
RIN−  
VCC  
GND  
NC  
Ground  
No Connect  
Top View  
Function Table  
Input  
Outputs  
RIN+  
RIN−  
ROUT  
L
H
L
L
H
H
H
Fail Safe Condition  
H = HIGH Logic Level  
L = LOW Logic Level  
Fail Safe = Open, Shorted, Terminated  
© 2002 Fairchild Semiconductor Corporation  
DS500730  
www.fairchildsemi.com  

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