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FIN1001_04

更新时间: 2024-10-27 03:36:55
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
7页 616K
描述
3.3V LVDS 1-Bit High Speed Differential Driver

FIN1001_04 数据手册

 浏览型号FIN1001_04的Datasheet PDF文件第2页浏览型号FIN1001_04的Datasheet PDF文件第3页浏览型号FIN1001_04的Datasheet PDF文件第4页浏览型号FIN1001_04的Datasheet PDF文件第5页浏览型号FIN1001_04的Datasheet PDF文件第6页浏览型号FIN1001_04的Datasheet PDF文件第7页 
December 2001  
Revised August 2004  
FIN1001  
3.3V LVDS 1-Bit High Speed Differential Driver  
General Description  
Features  
This single driver is designed for high speed interconnects  
utilizing Low Voltage Differential Signaling (LVDS) technol-  
ogy. The driver translates LVTTL signal levels to LVDS lev-  
els with a typical differential output swing of 350 mV which  
provides low EMI at ultra low power dissipation even at  
high frequencies. This device is ideal for high speed trans-  
fer of clock or data.  
Greater than 600Mbs data rate  
3.3V power supply operation  
0.5ns maximum differential pulse skew  
1.5ns maximum propagation delay  
Low power dissipation  
Power-Off protection  
The FIN1001 can be paired with its companion receiver,  
the FIN1002, or with any other LVDS receiver.  
Meets or exceeds the TIA/EIA-644 LVDS standard  
Flow-through pinout simplifies PCB layout  
5-Lead SOT23 package saves space  
Ordering Code:  
Order Number Package Number  
Package Description  
FIN1001M5  
MA05B  
MA05B  
5-Lead SOT23, JEDEC MO-178, 1.6mm [250 Units on Tape and Reel]  
5-Lead SOT23, JEDEC MO-178, 1.6mm [3000 Units on Tape and Reel]  
FIN1001M5X  
Pin Descriptions  
Connection Diagram  
Pin Name  
Description  
Pin Assignment for SOT23  
DIN  
DOUT+  
DOUT−  
VCC  
LVTTL Data Input  
Non-inverting LVDS Driver Output  
Inverting LVDS Driver Output  
Power Supply  
GND  
NC  
Ground  
No Connect  
Function Table  
Input  
Outputs  
DOUT−  
DIN  
DOUT+  
L
L
H
L
H
H
(Top View)  
H = HIGH Logic Level  
L = LOW Logic Level  
© 2004 Fairchild Semiconductor Corporation  
DS500721  
www.fairchildsemi.com  

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