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EMB16P04V PDF预览

EMB16P04V

更新时间: 2024-11-19 17:15:35
品牌 Logo 应用领域
杰力科技 - EXCELLIANCE /
页数 文件大小 规格书
7页 856K
描述
EDFN3X3

EMB16P04V 数据手册

 浏览型号EMB16P04V的Datasheet PDF文件第2页浏览型号EMB16P04V的Datasheet PDF文件第3页浏览型号EMB16P04V的Datasheet PDF文件第4页浏览型号EMB16P04V的Datasheet PDF文件第5页浏览型号EMB16P04V的Datasheet PDF文件第6页浏览型号EMB16P04V的Datasheet PDF文件第7页 
EMB16P04V  
P-Channel Logic Level Enhancement Mode Field Effect Transistor  
Product Summary:  
BVDSS  
-40V  
16mΩ  
-20A  
RDSON (MAX.)  
ID  
P-Channel MOSFET  
UIS, Rg 100% Tested  
Pb-Free Lead Plating & Halogen Free  
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C Unless Otherwise Noted)  
PARAMETERS/TEST CONDITIONS  
SYMBOL  
LIMITS  
±20  
-20  
UNIT  
Gate-Source Voltage  
VGS  
V
TC = 25 °C  
Continuous Drain Current  
ID  
TA = 25 °C  
-10  
A
TC = 100 °C  
-13  
Pulsed Drain Current1  
IDM  
IAS  
-80  
Avalanche Current  
-15  
L = 0.1mH, IAS=-15A, RG=25Ω  
L = 0.05mH  
Avalanche Energy  
EAS  
EAR  
11.25  
5.62  
21  
mJ  
W
Repetitive Avalanche Energy2  
TC = 25 °C  
Power Dissipation  
Power Dissipation  
PD  
TC = 100 °C  
8.3  
TA = 25 °C  
2.5  
PD  
W
°C  
TA = 100 °C  
1
Operating Junction & Storage Temperature Range  
Tj, Tstg  
-55 to 150  
THERMAL RESISTANCE RATINGS  
THERMAL RESISTANCE  
SYMBOL  
RJC  
TYPICAL  
MAXIMUM  
UNIT  
Junction-to-Case  
6
°C / W  
Junction-to-Ambient3  
50  
RJA  
1Pulse width limited by maximum junction temperature.  
2Duty cycle 1%  
2019/6/25  
p.1  

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