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EDJ2116DEBG PDF预览

EDJ2116DEBG

更新时间: 2024-11-28 12:48:03
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器双倍数据速率
页数 文件大小 规格书
33页 404K
描述
2G bits DDR3 SDRAM

EDJ2116DEBG 数据手册

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COVER  
DATA SHEET  
2G bits DDR3 SDRAM  
EDJ2108DEBG (256M words × 8 bits)  
EDJ2116DEBG (128M words × 16 bits)  
Specifications  
Features  
• Density: 2G bits  
• Organization  
• Double-data-rate architecture: two data transfers per  
clock cycle  
• The high-speed data transfer is realized by the 8 bits  
prefetch pipelined architecture  
• Bi-directional differential data strobe (DQS and /DQS)  
is transmitted/received with data for capturing data at  
the receiver  
• DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
• Differential clock inputs (CK and /CK)  
— 32M words × 8 bits × 8 banks (EDJ2108DEBG)  
— 16M words × 16 bits × 8 banks (EDJ2116DEBG)  
• Package  
— 78-ball FBGA (EDJ2108DEBG)  
— 96-ball FBGA (EDJ2116DEBG)  
— Lead-free (RoHS compliant) and Halogen-free  
• Power supply: VDD, VDDQ = 1.5V ± 0.075V  
• Data rate  
• DLL aligns DQ and DQS transitions with CK transitions  
— 2133Mbps/1866Mbps/1600Mbps/1333Mbps (max)  
• Spread Spectrum Clock (SSC)  
— Sweep rate: down spread 1% (20kHz to 60kHz)  
• 1KB page size (EDJ2108DEBG)  
— Row address: A0 to A14  
— Column address: A0 to A9  
• 2KB page size (EDJ2116DEBG)  
— Row address: A0 to A13  
• Commands entered on each positive CK edge; data  
and data mask referenced to both edges of DQS  
• Data mask (DM) for write data  
• Posted /CAS by programmable additive latency for  
better command and data bus efficiency  
• On-Die Termination (ODT) for better signal quality  
— Synchronous ODT  
— Dynamic ODT  
— Asynchronous ODT  
— Column address: A0 to A9  
• Multi Purpose Register (MPR) for pre-defined pattern  
read out  
• ZQ calibration for DQ drive and ODT  
• /RESET pin for Power-up sequence and reset function  
• SRT range:  
• Eight internal banks for concurrent operation  
• Interface: SSTL_15  
• Burst length (BL): 8 and 4 with Burst Chop (BC)  
• Burst type (BT):  
— Sequential (8, 4 with BC)  
— Interleave (8, 4 with BC)  
• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11, 13, 14  
• /CAS Write Latency (CWL): 5, 6, 7, 8, 9, 10  
• Precharge: auto precharge option for each burst  
access  
— Normal/extended  
• Programmable Output driver impedance control  
• Seamless BL4 access with bank-grouping  
— Applied only for DDR3-1333 and 1600  
• Driver strength: RZQ/7, RZQ/6 (RZQ = 240)  
• Refresh: auto-refresh, self-refresh  
• Refresh cycles  
— Average refresh period  
7.8µs at 0°C TC +85°C  
3.9µs at +85°C < TC +95°C  
• Operating case temperature range  
— TC = 0°C to +95°C  
Document. No. E1712E60 (Ver. 6.0)  
Date Published October 2013 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
©Elpida Memory, Inc. 2010-2013  

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