Datasheet > EDJ4204EFBG

EDJ4204EFBG

更新时间： 2024-11-29 12:24:55

品牌	Logo	应用领域
尔必达 - ELPIDA		时钟
页数	文件大小	规格书
29页	656K
描述
Differential clock inputs

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中文翻译

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数据手册

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EDJ4204EFBG 数据手册

COVER

PRELIMINARY DATA SHEET

4G bits DDR3L SDRAM

EDJ4204EFBG (1024M words × 4 bits)

EDJ4208EFBG (512M words × 8 bits)

EDJ4216EFBG (256M words × 16 bits)

Specifications

Features

• Density: 4G bits

• Organization

• Double-data-rate architecture: two data transfers per

clock cycle

• The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

— 128M words × 4 bits × 8 banks (EDJ4204EFBG)

— 64M words × 8 bits × 8 banks (EDJ4208EFBG)

— 32M words × 16 bits × 8 banks (EDJ4216EFBG)

• Package

— 78-ball FBGA (EDJ4204EFBG, EDJ4208EFBG)

— 96-ball FBGA (EDJ4216EFBG)

— Lead-free (RoHS compliant) and Halogen-free

• Power supply: 1.35V (typ)

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK transitions

— VDD = 1.283V to 1.45V

— Backward compatible for VDD, VDDQ

= 1.5V 0.075V

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Data mask (DM) for write data

• Data rate

— 1600Mbps/1333Mbps (max)

• 1KB page size

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

• On-Die Termination (ODT) for better signal quality

— Synchronous ODT

— Row address: A0 to A15

— Column address: A0 to A9, A11 (EDJ4204EFBG)

A0 to A9 (EDJ4208EFBG)

— Dynamic ODT

— Asynchronous ODT

• Multi Purpose Register (MPR) for pre-defined pattern

read out

• 2KB page size (EDJ4216EFBG)

— Row address: A0 to A14

• ZQ calibration for DQ drive and ODT

• Programmable Partial Array Self-Refresh (PASR)

• /RESET pin for Power-up sequence and reset function

• SRT range:

— Normal/extended

• Programmable Output driver impedance control

— Column address: A0 to A9

• Eight internal banks for concurrent operation

• Burst length (BL): 8 and 4 with Burst Chop (BC)

• Burst type (BT):

— Sequential (8, 4 with BC)

— Interleave (8, 4 with BC)

• /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11

• /CAS Write Latency (CWL): 5, 6, 7, 8

• Precharge: auto precharge option for each burst

access

• Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)

• Refresh: auto-refresh, self-refresh

• Refresh cycles

— Average refresh period

7.8µs at 0°C ≤ TC ≤ +85°C

3.9µs at +85°C < TC ≤ +95°C

• Operating case temperature range

— TC = 0°C to +95°C

Document. No. E1922E11 (Ver. 1.1)

Date Published September 2012 (K) Japan

Printed in Japan

URL: http://www.elpida.com

12 3 4 5 6 7...29

中文翻译

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与EDJ4204EFBG相关器件

型号	品牌	获取价格	描述	数据表
EDJ4204EFBG-DJ-F	ELPIDA	获取价格	Differential clock inputs
EDJ4204EFBG-GN-F	ELPIDA	获取价格	Differential clock inputs
EDJ4208BFBG-DJ-F	ELPIDA	获取价格	Differential clock inputs
EDJ4208BFBG-GN-F	ELPIDA	获取价格	Differential clock inputs
EDJ4208BFBG-JS-F	ELPIDA	获取价格	Differential clock inputs
EDJ4208EASE-DJ-F	ELPIDA	获取价格	DDR DRAM, 512MX8, 0.255ns, CMOS, PBGA78, HALOGEN FREE AND ROHS COMPLIANT, FBGA-78
EDJ4208EFBG	ELPIDA	获取价格	4G bits DDR3L SDRAM
EDJ4208EFBG-DJ-F	ELPIDA	获取价格	Differential clock inputs
EDJ4208EFBG-GN-F	ELPIDA	获取价格	Differential clock inputs
EDJ4216BASE	ELPIDA	获取价格	4G bits DDR3 SDRAM

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