EDJ5304BASE-8A-E

更新时间： 2024-11-28 12:20:55

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
130页	1562K
描述
512M bits DDR3 SDRAM

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中文翻译

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数据手册

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EDJ5304BASE-8A-E 数据手册

PRELIMINARY DATA SHEET

512M bits DDR3 SDRAM

EDJ5304BASE (128M words × 4 bits)

EDJ5308BASE (64M words × 8 bits)

EDJ5316BASE (32M words × 16 bits)

Features

Specifications

• Density: 512M bits

• Organization

⎯ 16M words × 4 bits × 8 banks (EDJ5304BASE)

⎯ 8M words × 8 bits × 8 banks (EDJ5308BASE)

⎯ 4M words × 16 bits × 8 banks (EDJ5316BASE)

• Package

• Double-data-rate architecture; two data transfers per

clock cycle

• The high-speed data transfer is realized by the 8 bits

prefetch pipelined architecture

• Bi-directional differential data strobe (DQS and /DQS)

is transmitted/received with data for capturing data at

the receiver

⎯ 78-ball FBGA (EDJ5304/5308BASE)

⎯ 96-ball FBGA (EDJ5316BASE)

⎯ Lead-free (RoHS compliant)

• Power supply: VDD, VDDQ = 1.5V 0.075V

• Data rate

⎯ 1333Mbps/1066Mbps/800Mbps (max.)

• 1KB page size (EDJ5304/5308BASE)

⎯ Row address: A0 to A12

• DQS is edge-aligned with data for READs; center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

and data mask referenced to both edges of DQS

• Data mask (DM) for write data

• Posted /CAS by programmable additive latency for

better command and data bus efficiency

⎯ Column address: A0 to A9, A11 (EDJ5304BASE)

A0 to A9 (EDJ5308BASE)

• On-Die Termination (ODT) for better signal quality

⎯ Synchronous ODT

⎯ Dynamic ODT

⎯ Asynchronous ODT

• Multi Purpose Register (MPR) for temperature read

out

• 2KB page size (EDJ5316BASE)

⎯ Row address: A0 to A11

⎯ Column address: A0 to A9

• Eight internal banks for concurrent operation

• Interface: SSTL_15

• Burst lengths (BL): 8 and 4 with Burst Chop (BC)

• Burst type (BT):

⎯ Sequential (8, 4 with BC)

• ZQ calibration for DQ drive and ODT

• Programmable Partial Array Self-Refresh (PASR)

• /RESET pin for Power-up sequence and reset

function

⎯ Interleave (8, 4 with BC)

• /CAS Latency (CL): 5, 6, 7, 8, 9, 10

• /CAS Write Latency (CWL): 5, 6, 7, 8

• Precharge: auto precharge option for each burst

access

• SRT range:

⎯ Normal/extended

⎯ Auto/manual self-refresh

• Programmable Output driver impedance control

• Driver strength: RZQ/7, RZQ/6 (RZQ = 240Ω)

• Refresh: auto-refresh, self-refresh

• Refresh cycles

⎯ Average refresh period

7.8μs at 0°C ≤ TC ≤ +85°C

3.9μs at +85°C < TC ≤ +95°C

• Operating case temperature range

⎯ TC = 0°C to +95°C

^{Document No. E0966E60 (Ver. 6.0)}This product became EOL in September, 2010.

Date Published July 2007 (K) Japan

Printed in Japan

URL: http://www.elpida.com

12 3 4 5 6 7...130

中文翻译

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与EDJ5304BASE-8A-E相关器件

型号	品牌	获取价格	描述	数据表
EDJ5304BASE-8C-E	ELPIDA	获取价格	512M bits DDR3 SDRAM
EDJ5304BASE-AC-E	ELPIDA	获取价格	512M bits DDR3 SDRAM
EDJ5304BASE-AE-E	ELPIDA	获取价格	512M bits DDR3 SDRAM
EDJ5304BASE-AG-E	ELPIDA	获取价格	512M bits DDR3 SDRAM
EDJ5304BASE-DG-E	ELPIDA	获取价格	512M bits DDR3 SDRAM
EDJ5304BASE-DJ-E	ELPIDA	获取价格	512M bits DDR3 SDRAM
EDJ5308AASE-AE-E	ELPIDA	获取价格	DDR DRAM, 64MX8, CMOS, PBGA78, ROHS COMPLIANT, MICRO, BGA-78
EDJ5308AASE-AG-E	ELPIDA	获取价格	DDR DRAM, 64MX8, CMOS, PBGA78, ROHS COMPLIANT, MICRO, BGA-78
EDJ5308AASE-DG-E	ELPIDA	获取价格	DDR DRAM, 64MX8, CMOS, PBGA78, ROHS COMPLIANT, MICRO, BGA-78
EDJ5308AASE-DJ-E	ELPIDA	获取价格	DDR DRAM, 64MX8, CMOS, PBGA78, ROHS COMPLIANT, MICRO, BGA-78

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