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EDJ5308AASE-DJ-E PDF预览

EDJ5308AASE-DJ-E

更新时间: 2024-11-29 20:49:31
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器双倍数据速率内存集成电路
页数 文件大小 规格书
4页 46K
描述
DDR DRAM, 64MX8, CMOS, PBGA78, ROHS COMPLIANT, MICRO, BGA-78

EDJ5308AASE-DJ-E 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:BGA,针数:78
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.28风险等级:5.84
访问模式:MULTI BANK PAGE BURST其他特性:AUTO/SELF REFRESH
JESD-30 代码:R-PBGA-B78JESD-609代码:e1
内存密度:536870912 bit内存集成电路类型:DDR DRAM
内存宽度:8功能数量:1
端口数量:1端子数量:78
字数:67108864 words字数代码:64000000
工作模式:SYNCHRONOUS组织:64MX8
封装主体材料:PLASTIC/EPOXY封装代码:BGA
封装形状:RECTANGULAR封装形式:GRID ARRAY
认证状态:Not Qualified自我刷新:YES
最大供电电压 (Vsup):1.575 V最小供电电压 (Vsup):1.425 V
标称供电电压 (Vsup):1.5 V表面贴装:YES
技术:CMOS端子面层:TIN SILVER COPPER
端子形式:BALL端子位置:BOTTOM
Base Number Matches:1

EDJ5308AASE-DJ-E 数据手册

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PRELIMINARY DATA SHEET  
512M bits DDR3 SDRAM  
EDJ5304AASE (128M words × 4 bits)  
EDJ5308AASE (64M words × 8 bits)  
EDJ5316AASE (32M words × 16 bits)  
Features  
Description  
The EDJ5304AASE is a 512M bits DDR3 SDRAM  
organized as 16,777,216 words × 4 bits × 8 banks.  
Power supply: VDD, VDDQ = 1.5V ± 0.075V  
Data rate: 1333Mbps/1066Mbps (max.)  
The EDJ5308AASE is a 512M bits DDR3 SDRAM  
organized as 8,388,608 words × 8 bits × 8 banks.  
They are packaged in 78-ball FBGA (µBGA) package.  
Double-data-rate architecture: two data transfers per  
clock cycle  
Bi-directional, differential data strobe (DQS and  
/DQS) is transmitted/received with data, to be used in  
capturing data at the receiver  
The EDJ5316AASE is a 512M bits DDR3 SDRAM  
organized as 4,194,304 words × 16 bits × 8 banks.  
It is packaged in 96-ball FBGA (µBGA) package.  
DQS is edge aligned with data for READs: center-  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge: data  
and data mask referenced to both edges of DQS  
8 internal banks for concurrent operation  
Data mask (DM) for write data  
Burst lengths (BL): 4, 8 and 4 with burst chop  
/CAS latency (CL): 5, 6, 7, 8, 9, 10  
/CAS write latency (CWL): 5, 6, 7, 8  
Auto precharge operation for each burst access  
Auto refresh and self refresh modes  
Average refresh period: 7.8µs  
1.5V I/O  
Posted CAS by programmable additive latency for  
better command and data bus efficiency  
On-Die-Termination for better signal quality  
Programmable Partial Array Self Refresh  
ZQ calibration for DQ drive and On-Die-Termination  
RESET-pin for Power-up sequence and reset-  
function  
FBGA (µBGA) package with lead free solder  
(Sn-Ag-Cu)  
RoHs compliant  
Document No. E0785E10 (Ver. 1.0)  
Date Published August 2005 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2005  

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