5秒后页面跳转
EDJ2116DEBG-JQ-F PDF预览

EDJ2116DEBG-JQ-F

更新时间: 2024-11-28 21:14:07
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器双倍数据速率
页数 文件大小 规格书
154页 2490K
描述
DDR DRAM, 128MX16, 0.195ns, CMOS, PBGA96, HALOGEN FREE AND ROHS COMPLIANT, FBGA-96

EDJ2116DEBG-JQ-F 技术参数

生命周期:Obsolete零件包装代码:BGA
包装说明:TFBGA,针数:96
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.73
访问模式:MULTI BANK PAGE BURST最长访问时间:0.195 ns
其他特性:AUTO/SELF REFRESHJESD-30 代码:R-PBGA-B96
JESD-609代码:e1长度:13.5 mm
内存密度:2147483648 bit内存集成电路类型:DDR DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:96
字数:134217728 words字数代码:128000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:组织:128MX16
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH
座面最大高度:1.2 mm自我刷新:YES
最大供电电压 (Vsup):1.575 V最小供电电压 (Vsup):1.425 V
标称供电电压 (Vsup):1.5 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:TIN SILVER COPPER端子形式:BALL
端子节距:0.8 mm端子位置:BOTTOM
宽度:9 mmBase Number Matches:1

EDJ2116DEBG-JQ-F 数据手册

 浏览型号EDJ2116DEBG-JQ-F的Datasheet PDF文件第2页浏览型号EDJ2116DEBG-JQ-F的Datasheet PDF文件第3页浏览型号EDJ2116DEBG-JQ-F的Datasheet PDF文件第4页浏览型号EDJ2116DEBG-JQ-F的Datasheet PDF文件第5页浏览型号EDJ2116DEBG-JQ-F的Datasheet PDF文件第6页浏览型号EDJ2116DEBG-JQ-F的Datasheet PDF文件第7页 
PRELIMINARY DATA SHEET  
2G bits DDR3 SDRAM  
EDJ2108DEBG-MQ (256M words 8 bits, 2133Mbps)  
EDJ2116DEBG-MQ (128M words 16 bits, 2133Mbps)  
EDJ2108DEBG-JQ (256M words 8 bits, 1866Mbps)  
EDJ2116DEBG-JQ (128M words 16 bits, 1866Mbps)  
Specifications  
Features  
Density: 2G bits  
Organization:  
Double-data-rate architecture: two data transfers per  
clock cycle  
The high-speed data transfer is realized by the 8 bits  
prefetch pipelined architecture  
32M words 8 bits 8 banks (EDJ2108DEBG)  
16M words 16 bits 8 banks (EDJ2116DEBG)  
Package:  
78-ball FBGA (EDJ2108DEBG)  
96-ball FBGA (EDJ2116DEBG)  
Lead-free (RoHS compliant) and Halogen-free  
Power supply: VDD, VDDQ 1.5V 0.075V  
Data rate  
Bi-directional differential data strobe (DQS and /DQS)  
is transmitted/received with data for capturing data at  
the receiver  
DQS is edge-aligned with data for READs; center-  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
2133Mbps/1866Mbps (max.)  
1KB page size (EDJ2108DEBG)  
Commands entered on each positive CK edge; data  
and data mask referenced to both edges of DQS  
Row address: A0 to A14  
Column address: A0 to A9  
Data mask (DM) for write data  
Posted /CAS by programmable additive latency for  
better command and data bus efficiency  
2KB page size (EDJ2116DEBG)  
Row address: A0 to A13  
Column address: A0 to A9  
Eight internal banks for concurrent operation  
Interface: SSTL_15  
On-Die Termination (ODT) for better signal quality  
Synchronous ODT  
Dynamic ODT  
Asynchronous ODT  
Multi Purpose Register (MPR) for pre-defined pattern  
read out  
Burst lengths (BL): 8 and 4 with Burst Chop (BC)  
Burst type (BT):  
Sequential (8, 4 with BC)  
ZQ calibration for DQ drive and ODT  
Interleave (8, 4 with BC)  
/RESET pin for Power-up sequence and reset  
function  
/CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11, 12  
/CAS Write Latency (CWL): 5, 6, 7, 8, 9  
No support CL13, CWL10  
SRT range:  
Normal/extended  
Programmable Output driver impedance control  
Precharge: auto precharge option for each burst  
access  
Driver strength: RZQ/7, RZQ/6, RZQ/5 (RZQ = 240)  
Refresh: auto-refresh, self-refresh  
Refresh cycles  
Average refresh period  
7.8s at 0C TC  85C  
3.9s at 85C TC  95C  
Operating case temperature range  
TC = 0C to +95C  
Document No. E1751E20 (Ver. 2.0)  
Date Published January 2012 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2011-2012  
 

与EDJ2116DEBG-JQ-F相关器件

型号 品牌 获取价格 描述 数据表
EDJ2116DEBG-JS-F ELPIDA

获取价格

2G bits DDR3 SDRAM
EDJ2116DEBG-MQ-F ELPIDA

获取价格

DDR DRAM, 128MX16, 0.18ns, CMOS, PBGA96, HALOGEN FREE AND ROHS COMPLIANT, FBGA-96
EDJ2116DEBG-MU-F ELPIDA

获取价格

2G bits DDR3 SDRAM
EDJ2116EEBG ELPIDA

获取价格

2G bits DDR3L SDRAM
EDJ2116EEBG-DJ-F ELPIDA

获取价格

Differential clock inputs
EDJ2116EEBG-GN-F ELPIDA

获取价格

Differential clock inputs
EDJ2116EEBG-JS-F ELPIDA

获取价格

Differential clock inputs
EDJ4204BFBG ELPIDA

获取价格

Differential clock inputs
EDJ4204BFBG-DJ-F ELPIDA

获取价格

Differential clock inputs
EDJ4204BFBG-GN-F ELPIDA

获取价格

Differential clock inputs