Datasheet > 存储 > DRAM> EDE5108ABSE-BE

EDE5108ABSE-BE

更新时间： 2024-09-19 06:55:55

品牌	Logo	应用领域
尔必达 - ELPIDA		动态存储器双倍数据速率
页数	文件大小	规格书
65页	667K
描述
512M bits DDR2 SDRAM for HYPER DIMM

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数据手册

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EDE5108ABSE-BE 数据手册

PRELIMINARY DATA SHEET

512M bits DDR2 SDRAM

for HYPER DIMM

EDE5108ABSE-BE, -AE (64M words × 8 bits)

Description

Features

The EDE5108AB is a 512M bits DDR2 SDRAM

• 1.8V power supply

organized as 16,777,216 words × 8 bits × 4 banks.

• Double-data-rate architecture: two data transfers per

clock cycle

It is packaged in 64-ball FBGA package.

• Bi-directional, differential data strobe (DQS and

/DQS) is transmitted/received with data, to be used in

capturing data at the receiver

• DQS is edge aligned with data for READs: center-

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge: data

and data mask referenced to both edges of DQS

• Four internal banks for concurrent operation

• Data mask (DM) for write data

• Burst lengths: 4, 8

• /CAS Latency (CL): 3, 4, 5

• Auto precharge operation for each burst access

• Auto refresh and self refresh modes

• 7.8µs average periodic refresh interval

• 1.8V (SSTL_18 compatible) I/O

• Posted CAS by programmable additive latency for

better command and data bus efficiency

• Off-Chip-Driver Impedance Adjustment and On-Die-

Termination for better signal quality

• Programmable RDQS, /RDQS output for making × 8

organization compatible to × 4 organization

• /DQS, (/RDQS) can be disabled for single-ended

Data Strobe operation.

• FBGA package with lead free solder

(Sn-Ag-Cu)

Document No. E0540E11 (Ver. 1.1)

Date Published February 2006 (K) Japan

URL: http://www.elpida.com

This Product became EOL in October, 2006.

Elpida Memory, Inc. 2004-2006

12 3 4 5 6 7...65

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