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EDE5108AGSE PDF预览

EDE5108AGSE

更新时间: 2024-09-18 22:05:27
品牌 Logo 应用领域
尔必达 - ELPIDA 动态存储器双倍数据速率
页数 文件大小 规格书
65页 657K
描述
512M bits DDR2 SDRAM

EDE5108AGSE 数据手册

 浏览型号EDE5108AGSE的Datasheet PDF文件第2页浏览型号EDE5108AGSE的Datasheet PDF文件第3页浏览型号EDE5108AGSE的Datasheet PDF文件第4页浏览型号EDE5108AGSE的Datasheet PDF文件第5页浏览型号EDE5108AGSE的Datasheet PDF文件第6页浏览型号EDE5108AGSE的Datasheet PDF文件第7页 
PRELIMINARY DATA SHEET  
512M bits DDR2 SDRAM  
EDE5104AGSE (128M words × 4 bits)  
EDE5108AGSE (64M words × 8 bits)  
Features  
Description  
The EDE5104AGSE is a 512M bits DDR2 SDRAM  
Power supply: VDD, VDDQ = 1.8V ± 0.1V  
organized as 33,554,432 words × 4 bits × 4 banks.  
Double-data-rate architecture: two data transfers per  
clock cycle  
The EDE5108AGSE is a 512M bits DDR2 SDRAM  
organized as 16,777,216 words × 8 bits × 4 banks.  
They are packaged in 60-ball FBGA (µBGA) package.  
Bi-directional, differential data strobe (DQS and  
/DQS) is transmitted/received with data, to be used in  
capturing data at the receiver  
DQS is edge aligned with data for READs: center-  
aligned with data for WRITEs  
Differential clock inputs (CK and /CK)  
DLL aligns DQ and DQS transitions with CK  
transitions  
Commands entered on each positive CK edge: data  
and data mask referenced to both edges of DQS  
Four internal banks for concurrent operation  
Data mask (DM) for write data  
Burst lengths: 4, 8  
/CAS Latency (CL): 3, 4, 5  
Auto precharge operation for each burst access  
Auto refresh and self refresh modes  
Average refresh period  
7.8µs at 0°C TC ≤ +85°C  
3.9µs at +85°C < TC ≤ +95°C  
SSTL_18 compatible I/O  
Posted CAS by programmable additive latency for  
better command and data bus efficiency  
Off-Chip-Driver Impedance Adjustment and On-Die-  
Termination for better signal quality  
Programmable RDQS, /RDQS output for making × 8  
organization compatible to × 4 organization  
/DQS, (/RDQS) can be disabled for single-ended  
Data Strobe operation.  
FBGA (µBGA) package with lead free solder  
(Sn-Ag-Cu)  
RoHS compliant  
Document No. E0715E20 (Ver. 2.0)  
Date Published July 2005 (K) Japan  
Printed in Japan  
URL: http://www.elpida.com  
Elpida Memory, Inc. 2005  

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