CY7C9335-400AC

更新时间： 2024-11-29 22:22:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		控制器
页数	文件大小	规格书
7页	147K
描述
SMPTE-259M/DVB-ASI Descrambler/Framer-Controller

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中文翻译

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数据手册

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CY7C9335-400AC 数据手册

CY7C9335

SMPTE-259M/DVB-ASI

Descrambler/Framer-Controller

The inputs of the CY7C9335 are designed to be directly mated

to a CY7B9334 HOTLink receiver, which converts the

SMPTE-259M compatible high-speed serial data stream into

10-bit parallel characters.

Features

Fully compatible with SMPTE-259M

•

— SMPTE-125M compliant for 4:2:2 component video

— SMPTE-244M compliant for 4fsc composite video

Fully compatible with DVB-ASI

Operates from a single +5V or 5V supply

100-pin TQFP package

This device performs both TRS (sync) detection and framing,

data descrambling with the SMPTE-259M X + X + 1 algo-

rithm, and NRZI-to-NRZ decoding. These functions operate at

any character rate from 16 to 40 MHz. For those systems op-

erating with non-SMPTE-259M compliant video streams (or for

diagnostic purposes), the descrambler and NRZI decoding

functions can be disabled.

•

−

Decodes 10-bitparallel digital streams for any rate from

16 40 M characters/sec (160 400 Mbits/sec serial)

−

Operates with CY7B9334 SMPTE HOTLink™ deserializ-

er/receiver

X + X + 1 descrambler and NRZI-to-NRZ decoder may

be bypassed for raw data output

•

DVB-ASI Operation

The CY7C9335 also contains the necessary multiplexers, con-

trol inputs and outputs, to control a DVB-ASI compliant video

stream. DVB-ASI operation is enabled through activation of a

single input signal. This allows a single serial-to-parallel input

port to support both SMPTE and DVB data streams under soft-

ware or hardware control.

Functional Description

SMPTE-259M Operation

The CY7C9335 is a CMOS integrated circuit designed to de-

code SMPTE-125M and SMPTE-244M bit-parallel digital char-

acters (or other data formats) using the SMPTE-259M decod-

ing rules. Following decoding, the characters are framed by

locating the 30-bit TRS pattern in the parallel character

stream. The framed characters are then output.

In DVB-ASI mode the CY7C9335 automatically enables both

the 8B/10B decoder and multi-byte framer present in the

CY7B9334 receiver/deserializer. All error detection, fill, and

command codes are detected and output by the CY7C9335.

The CY7C9335 operates from a single +5V or −5V supply. It is

available in a 100-pin TQFP space saving package.

Logic Block Diagram

D₉(RVS)

R F

D₈

D₇

D₆

A/B

P D₉(SVS)

PD₈

D₅

P D₇

D₄

P D₆

D₃

D₂

P D₅

P D₄

D₁

P D₃

D₀(SC/D)

P D₂

PD₁

PD₀(SC/D)

SYNC_EN

BYPASS

DVB_EN

H _ S Y N C

S Y N C _ E R R

CKR

O E

HOTLink is a trademark of Cypress Semiconductor Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

March 19, 1999

12 3 4 5 6 7

中文翻译

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与CY7C9335-400AC相关器件

型号	品牌	获取价格	描述	数据表
CY7C9335-40AC	ETC	获取价格	SMPTE
CY7C9335-40JC	ETC	获取价格	SMPTE
CY7C9335A	CYPRESS	获取价格	SMPTE-259M/DVB-ASI Descrambler/Framer-Controller
CY7C9335A-270AXC	CYPRESS	获取价格	Telecom Circuit, 1-Func, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, MS-026, TQFP-100
CY7C9335A-270AXCT	CYPRESS	获取价格	Telecom Circuit, 1-Func, CMOS, PQFP100, 14 X 14 MM, 1.40 MM HEIGHT, MS-026, TQFP-100
CY7C9536B	CYPRESS	获取价格	OC-48/STM-16 Framer with VC - POSIC2GVC⑩
CY7C9536B-BLC	CYPRESS	获取价格	OC-48/STM-16 Framer with VC - POSIC2GVC⑩
CY7C9536B-BLI	CYPRESS	获取价格	OC-48/STM-16 Framer with VC - POSIC2GVC⑩
CY7C9537B	CYPRESS	获取价格	OC-48/STM-16 Framer-POSIC2G
CY7C9537B-BLC	CYPRESS	获取价格	OC-48/STM-16 Framer-POSIC2G

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