CY7C954ADX
ATM HOTLink® Transceiver
provides enhanced levels of technology, functionality, and
integration over the field proven CY7B923/933 HOTLink.
Features
• Second-generation HOTLink® technology
The transmit section of the CY7C954ADX HOTLink has been
configured to accept 8-bit data characters on each clock cycle,
and store the parallel data into an internal Transmit FIFO. Data
is read from the Transmit FIFO and is encoded using an
embedded 8B/10B encoder to improve its serial transmission
characteristics. These encoded characters are then serialized
and output from two PECL (ECL referenced to +5.0V)-
compatible differential transmission line drivers at a bit-rate of
10 times the input reference clock.
• UTOPIA levels I- and II-compatible host bus interface
• Three-bit Multi-PHY address capability built-in
• Three user-selectable Start-Of-Cell marker/indicators
• Embedded 256-character synchronous FIFOs
• Built-in ATM Header Error Control (HEC)
• Automatic Transmit-HEC insertion and Receiver-HEC
check
• FIFO cell-level flushing of invalid ATM cells
The receive section of the CY7C954ADX HOTLink accepts a
serial bit-stream from one of two PECL-compatible differential
line receivers and, using a completely integrated PLL Clock
Synchronizer, recovers the timing information necessary for
data reconstruction. The recovered bit stream is deserialized
and framed into characters, 8B/10B decoded, and checked for
transmission errors. Recovered decoded characters are
reconstructed into 8-bit data characters, written to an internal
Receive FIFO, and presented to the destination host system.
• ATM Forum, Fibre Channel, and ESCON®-compliant
8B/10B encoder/decoder
• 50- to 200-MBaud serial signaling rate
• Internal PLLs with no external phase-locked loop (PLL)
components
• Dual differential pseudo-ECL (PECL)-compatible serial
inputs
• Dual differential PECL-compatible serial outputs
• Compatiblewith fiber-optic modules and copper cables
• Built-In Self-Test (BIST) for link testing
• Link Quality Indicator
For those systems requiring even greater FIFO storage
capability, external FIFOs may be directly coupled to the
CY7C954ADX device through the parallel interface without
additional glue-logic for single PHY connections.
• Single +5.0V ±10% supply
The TTL parallel I/O interface may be configured as either a
FIFO (configurable for UTOPIA emulation or for depth
expansion through external FIFOs) or as a pipeline register
extender. The FIFO configurations are optimized for transport
of time-independent (asynchronous) 8-bit character-oriented
data across a link. A Built-In Self-Test (BIST) pattern generator
and checker allows for at-speed testing of the high-speed
serial data paths in both the transmit and receive sections, and
across the interconnecting links.
• 100-pin TQFP
• 0.35µ CMOS technology
Functional Description
The 200-MBaud CY7C954ADX HOTLink Transceiver is a
point-to-point communications building block allowing the
transfer of data over high-speed serial links (optical fiber,
balanced, and unbalanced copper transmission lines) at
speeds ranging between 50 and 200 MBaud. The transmit
section accepts parallel data of selectable width and converts
it to serial data, while the receiver section accepts serial data
and converts it to parallel data of selectable width. Figure 1
illustrates typical connections between two independent host
systems and corresponding CY7C954ADX parts. As a
second-generation HOTLink device, the CY7C954ADX
HOTLink devices are ideal for a variety of applications where
parallel interfaces can be replaced with high-speed, point-to-
point serial links. Some applications include interconnecting
workstations, backplanes, servers, mass storage, and video
transmission equipment.
Transmit
Data
Data
Receive
Serial Link
Control
Control
Status
CY7C954ADX
CY7C954ADX
Status
Serial Link
Data
Transmit
Receive
Data
Figure 1. HOTLink System Connections
Cypress Semiconductor Corporation
Document #: 38-02007 Rev. *A
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised November 11, 2002
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