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CY7C955 PDF预览

CY7C955

更新时间： 2024-11-10 22:22:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 异步传输模式ATM
页数 文件大小 规格书
78页 464K
描述
AX⑩ ATM-SONET/SDH Transceiver

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中文翻译

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CY7C955 数据手册

 浏览型号CY7C955的Datasheet PDF文件第2页浏览型号CY7C955的Datasheet PDF文件第3页浏览型号CY7C955的Datasheet PDF文件第4页浏览型号CY7C955的Datasheet PDF文件第5页浏览型号CY7C955的Datasheet PDF文件第6页浏览型号CY7C955的Datasheet PDF文件第7页 
PRELIMINARY  
CY7C955  
AX™ ATM-SONET/SDH Transceiver  
— Line Far End Receive Failure  
— Line Alarm Indication Signal  
— B1 Parity Error  
Features  
WAN and LAN ATM physical layer device  
•
•
Providescompletephysicallayer transportofATMcells  
at:  
— Loss Of Cell Alignment  
— Loss Of Receive Data  
— STS 3c/ STM 1 rate of 155.52 MHz  
−
−
— STS 1 rate of 51.84 MHz  
−
Controller interface for internal interrupt and  
configuration registers including:  
•
Compliant with ATM Forum User Network Interface 3.1  
specification  
UTOPIA ATM interface  
ATM cell processing including:  
— HEC generation/verification  
•
— Error monitoring  
— Status indication  
— Device configuration  
•
•
0.65 Low Power CMOS  
•
µ
— Cell scrambling/descrambling  
— Rate adaption/idle cell filtering  
— Local Flow Control  
• 128-pin PQFP  
Functional Description  
The Cypress Semiconductor CY7C955 is a Transceiver chip  
designed to carry ATM cells across SONET/SDH systems.  
— Cell alignment  
SONET frame processing including:  
•
On the transmit side, ATM cells coming from the Utopia inter-  
face are being mapped into SONET/SDH frames and then se-  
rialized for transmission over fiber or twisted pair (through an  
optical module or an equalizer chip).  
— Compliant with Bellcore GR 253, I.432,  
−
T1.105, and G.709 for Jitter Tolerance and Jitter  
Generation  
— Frame generation/recovery  
On the receive side, serial SONET/SDH datastreams coming  
from an optical module or an equalizer chip are being recov-  
ered by the intergrated clock and data recovery phase-locked  
loop, framed, processed, and presented as parallel ATM cells  
on the Receive Utopia Interface.  
— SONET scrambling/descrambling  
— Frequency justification/pointer processing  
Complete line interface including:  
— Clock and data recovery  
•
•
The CY7C955 can be used in a Network Interface Card (NIC)  
design to connect the segmentation and Reassembly (SAR)  
chip to the optical modules or equalizer chip.  
— Transmit timing derived from receiver or byte-rate  
source  
— SONET compliant PLL  
— 100K PECL compatible I/O  
Alarm indications including:  
— Loss Of Signal  
The CY7C955 can also be used in work group or enterprise  
switches to connect the I/O FIFOs of the switch fabric to the  
optical module or equalizer in the interface boards.  
The applications of the CY7C955 include adapters, switches,  
routers, hubs, and proprietary systems.  
— Out Of Frame, Loss Of Frame  
TABLE OF CONTENTS  
Features  
1
1
Functional Description  
Pin Descriptions  
2
Pin Configuration  
7
Description  
8
Transmit Section  
8
Receive Section  
10  
12  
16  
17  
18  
60  
61  
61  
61  
Controller Interface (CI)  
Loopback Operation  
SONET Overhead Description  
CY7C955 Register Map  
Electrical Characteristics  
Capacitance  
AC Test Loads and Waveforms  
Switching Characteristics  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
November 29, 1999  
1234567...78

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