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CY7C955 PDF预览

CY7C955

更新时间： 2024-02-13 17:35:10
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 异步传输模式ATM
页数 文件大小 规格书
78页 464K
描述
AX⑩ ATM-SONET/SDH Transceiver

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CY7C955 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：QFP包装说明：FQFP, QFP128(UNSPEC)
针数：128Reach Compliance Code：not_compliant
HTS代码：8542.39.00.01风险等级：5.92
Is Samacsys：N应用程序：ATM;SDH;SONET
JESD-30 代码：R-PQFP-G128JESD-609代码：e0
长度：20 mm功能数量：1
端子数量：128最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：FQFP封装等效代码：QFP128(UNSPEC)
封装形状：RECTANGULAR封装形式：FLATPACK, FINE PITCH
峰值回流温度（摄氏度）：225电源：5 V
认证状态：Not Qualified座面最大高度：3.32 mm
子类别：ATM/SONET/SDH ICs标称供电电压：5 V
表面贴装：YES技术：CMOS
电信集成电路类型：ATM/SONET/SDH TRANSCEIVER温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：14 mm
Base Number Matches：1

CY7C955 数据手册

 浏览型号CY7C955的Datasheet PDF文件第1页浏览型号CY7C955的Datasheet PDF文件第2页浏览型号CY7C955的Datasheet PDF文件第3页浏览型号CY7C955的Datasheet PDF文件第5页浏览型号CY7C955的Datasheet PDF文件第6页浏览型号CY7C955的Datasheet PDF文件第7页 
PRELIMINARY  
CY7C955  
Receive Clock Recovery (continued)  
Name  
Pin  
I/O  
Description  
RXDO±  
22−23  
Differential Out Receive Output Data: These differential outputs represent the retimed version of the  
input data stream (RXD±) in normal mode and the buffered version of the input datas-  
tream (RXD±) in bypass mode. This output pair can be used as inputs to decision  
feedback equalizers to correct for baseline wander. RXDO can be turned off to save  
power by setting RXDOD (Reg−04H, bit 7) to 1.  
RRCLK±  
33−34  
Differential In  
Receive Clock: These inputs are used to clock in the differential data (RXD±) when the  
Receive clock recovery block is bypassed (RBYP=HIGH). If RBYP is LOW, RRCLK is  
multiplied by 8, 24, or 8/3 depending on the setting of RREFSEL (Reg−07H, bit 0) and  
use as a reference for the Receiver PLL. Refer to the section on “Interface Termination  
and Bias of Schemes” for connection examples to these pins.  
RBYP  
41  
Input  
Receive Clock Bypass: When this input is HIGH the Receiver clock recovery block is  
bypassed. In this mode the device does not recover clock and data from the Receive  
input data stream (RXD±) but instead uses the RRCLK± inputs to clock the differential  
data into the device. When this input is LOW the Receiver clock recovery block recovers  
the clock and data from the input data stream. In this mode a byte-rate clock is expected  
on the RRCLK± inputs.  
RCLK  
RFP  
57  
58  
Output  
Output  
Receive Byte Reference: Provides a byte-rate reference derived from the recovered  
bit- rate Receive clock. RALM, RCP, and RGFC are aligned with this clock.  
Receive Frame Reference: This output provides a frame-rate reference clock aligned  
to the SONET/SDH frame alignment bytes. RFP will pulse HIGH for one RCLK cycle  
every 125 seconds even at OOF and LOF situations.  
LF+  
42  
Input  
Input  
NC. This pin is for factory testing only.  
LF–, LFO  
43, 44  
These are the PLL filter pins. Connect a 0.47-µF capacitor across LF– and LFO.  
Receive ATM Interface  
Name  
Pin  
I/O  
Description  
RGFC  
59  
Output  
Receive Generic Flow Control: This output provides the four bits of the current ATM  
cell header GFC locations at each successive RCLK pulse. The RCP output indicates  
the first GFC bit location. This output is forced LOW if the ATM Cell Processor has lost  
cell delineation.  
RALM  
RCP  
63  
60  
Output  
Output  
Receive Interrupt: This active HIGH signal is aligned with the RCLK byte-rate clock and  
signals the presence of LAIS, PAIS, LOS, LOF, LOP, or LCD.  
Receive Start Of GFC: This output indicates the first bit of the GFC presented on the  
RGFC output. This output goes HIGH for 1 RCLK cycle 6 byte times after the corre-  
sponding cell is written into the Receive FIFO.  
Receive Utopia Interface  
Name  
Pin No I/O  
Description  
RDAT[7:0] 70−71  
74−79  
Output  
Output  
Output  
Input  
Receive Utopia Data: Byte-wide data driven from the PHY to ATM layer. RDAT[7] is the  
MSB  
RPRTY  
RSOC  
RFCLK  
82  
83  
67  
Receive Utopia Data Parity: Data parity calculated over RDAT[7:0]. Odd parity is as-  
sumed unless the TXPRTY bit is set to even parity by Reg−50H, bit 6.  
Receive Utopia Start of Cell: Asserted HIGH when RDAT[7:0] contains the first byte of  
an ATM cell.  
Receive Utopia Clock: Data transfer clock. Data is transferred from the AX on the rising  
edge of RFCLK when RRDENB is asserted (LOW).  
RRDENB  
RCA  
68  
69  
Input  
Receive Utopia Enable: Enables the RFCLK input for data transfers from the AX.  
Output  
Receive Utopia Cell Available: An active signal indicates that the Receive FIFO con-  
tains at least 1 or 4 more bytes of data. RCA is controlled by RCAINV (Reg−01H, bit  
2) and RCALEVEL0 (Reg−59H, bit 2).  
4
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