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CY7C964-GMB

更新时间: 2024-11-11 00:00:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 总线控制器微控制器和处理器外围集成电路
页数 文件大小 规格书
6页 102K
描述
Bus Interface Logic Circuit

CY7C964-GMB 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:PGA包装说明:CAVITY UP, CERAMIC, PGA-68
针数:68Reach Compliance Code:not_compliant
风险等级:5.91地址总线宽度:8
外部数据总线宽度:8JESD-30 代码:S-CPGA-P68
JESD-609代码:e0长度:27.94 mm
端子数量:68最高工作温度:125 °C
最低工作温度:-55 °C封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:PGA封装等效代码:PGA68,11X11
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
认证状态:Not Qualified筛选级别:38535Q/M;38534H;883B
座面最大高度:5.207 mm子类别:Bus Controllers
最大压摆率:25 mA标称供电电压:5 V
表面贴装:NO技术:CMOS
温度等级:MILITARY端子面层:Tin/Lead (Sn/Pb)
端子形式:PIN/PEG端子节距:2.54 mm
端子位置:PERPENDICULAR处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:27.94 mmuPs/uCs/外围集成电路类型:BUS CONTROLLER, VME
Base Number Matches:1

CY7C964-GMB 数据手册

 浏览型号CY7C964-GMB的Datasheet PDF文件第2页浏览型号CY7C964-GMB的Datasheet PDF文件第3页浏览型号CY7C964-GMB的Datasheet PDF文件第4页浏览型号CY7C964-GMB的Datasheet PDF文件第5页浏览型号CY7C964-GMB的Datasheet PDF文件第6页 
64  
fax id: 5604  
CY7C964  
Bus Interface Logic Circuit  
ler. In every case, the controllers provide the control and timing  
signals to the Bus Interface Logic Circuit as it acts as a bridge  
between the VMEbus and the Local bus.  
Features  
• Comparators, counters, latches, and drivers minimize  
logic requirements for a variety of multiplexed and  
non-multiplexed buses  
Application with VMEbus Architecture  
• Directly drives VMEbus address and data signals  
• 8-bit comparator for slave address decoding  
• Flexible interface optimized for VMEbus applications  
• Companion device to Cypress VMEbus family of com-  
ponents  
• Replaces multiple SSI/MSI components  
• Cascadable  
• 64-pin QFP and 68-pin PGA packages  
Use with Cypress VMEbus Controllers  
The CY7C964 Bus Interface Logic Circuit is a seamless inter-  
face between the VIC068A/VIC64 and the VMEbus signals.  
The device functions equally well in the established 32-bit  
VMEbus arena and the new 64-bit VMEbus standard. The de-  
vice contains three 8-bit counters to fulfill the functions of Block  
counters, and DMA counters as implied by the D64 portion of  
the VMEbus specification. It also contains the necessary mul-  
tiplexing logic to allow the 64-bit-wide VMEbus path to be fun-  
nelled to and from the 32-bit local bus. Control circuitry is in-  
cluded to manage the switching of the 32-bit address bus  
during normal (32-bit) operations, and during MBLT (64-bit)  
operations. The on-chip drivers are capable of driving the  
VMEbus directly (48 mA).  
• See the VMEbus Interface Handbook for more informa-  
tion  
Functional Description  
The CY7C964 integrates several space-consuming functions  
into one small package, freeing board space for the implemen-  
tation of added-value board features. It contains counters,  
comparators, latches, and drivers configured to be of value to  
implementors of any backplane interface with address and  
data buses, particularly VMEbus interfaces. The on-chip driv-  
ers are suitable for driving the VMEbus directly. The CY7C964  
is ideal in applications where high-performance and real es-  
tate are primary concerns.  
Use in Other VMEbus Controller Implementations  
The CY7C964 circuitry is designed to be of use to designers  
of VMEbus circuitry, including VSB (VME subsystem bus) and  
designs not requiring the features of the Cypress VIC068A,  
VIC64, CY7C960, and CY7C961. The logic diagram includes  
general-purpose blocks of comparators, counters, and latches  
that can be controlled using the flexible control interface to  
allow many different options to be implemented. Although the  
device is packaged in a small 64-pin package, the use of mul-  
tiplexed input and output pins provides access to the many  
internal functions, thus saving external circuitry.  
Although having many applications, the Bus Interface Logic  
Circuit is an ideal companion part to Cypress’s VMEbus family  
of components, the VIC068A, VIC64, the CY7C960, and  
CY7C961. It is intended to drive the address and data buses,  
so three or four of these small devices are needed per control-  
Pin Configuration  
PQFP/CQFP/TQFP  
Top View  
48  
47  
46  
45  
44  
GND  
LD0  
LA0  
GND  
LD7  
LDS  
1
2
3
4
5
DENIN*  
DENIN1*  
LAEN  
FC1  
STROBE*  
43  
42  
41  
6
7
8
MWB*  
LCOUT*  
GND  
VCOMP*  
VCOUT*  
LADO  
LADI  
LEDI  
LEDO  
A7  
LCIN*  
VCIN*  
VCC  
BLT*  
D64  
40  
39  
9
10  
38  
37  
36  
11  
12  
13  
DENO*  
ABEN*  
D0  
35  
34  
14  
15  
A0  
33  
16  
GND  
GND  
C964-1  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
November 1992 – Revised December 4, 1997  

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