Datasheet > CY7C9915-5JXI

CY7C9915-5JXI

更新时间： 2024-11-11 04:38:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
14页	309K
描述
3.3V Programmable Skew Clock Buffer

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CY7C9915-5JXI 数据手册

CY7C9915

PRELIMINARY

3.3V Programmable Skew Clock Buffer

Features

Functional Description

• All output pair skew <100 ps (typical)

• Input Frequency Range: 3.75 MHz to 150 MHz

• Output Frequency Range: 3.75 MHz to 150 MHz

• User-selectable output functions

— Selectable skew to 18 ns

The CY7C9915 RoboClock is a 150-MHz Low-voltage

Programmable Skew Clock Buffer that offers user-selectable

control over system clock functions. This multiple-output clock

driver provides the system integrator with functions necessary

to optimize the timing of high-performance computer systems.

Eight individual drivers, arranged as four pairs of user-control-

lable outputs, can each drive terminated transmission lines

with impedances as low as 50Ω while delivering minimal and

specified output skews and full-swing logic levels (LVTTL).

— Inverted and non-inverted

— Operation at ¹⁄₂and ¹⁄₄input frequency

Each output can be hardwired to one of nine delay or function

configurations. Delay increments of 0.42 to 1.6 ns are deter-

mined by the operating frequency with outputs able to skew up

to ±6 time units from their nominal “zero” skew position. The

completely integrated PLL allows external load and trans-

mission line delay effects to be canceled. When this “zero

delay” capability of the LVPSCB is combined with the

selectable output skew functions, the user can create

output-to-output delays of up to ±12 time units.

— Operation at 2x and 4x input frequency (input as low

as 3.75 MHz)

• Zero input-to-output delay

• 3.3V power supply

• ± 3.0% Output Duty Cycle Distortion

• LVTTL outputs drive 50Ω terminated lines

• Low operating current

Divide-by-two and divide-by-four output functions are provided

for additional flexibility in designing complex clock systems.

When combined with the internal PLL, these divide functions

allow distribution of a low-frequency clock that can be multi-

plied by two or four at the clock destination. This facility

minimizes clock distribution difficulty while allowing maximum

system clock speed and flexibility.

• 32-pin PLCC package

• Jitter < 100ps peak-to-peak (< 15 ps RMS)

Block Diagram

Pin Configuration

TEST

PHASE

VCO AND

TIME UNIT

FREQ

DET

FILTER

REF

GENERATOR

31 30

3F1

4F0

4F1

2F0

GND

1F1

4Q0

4Q1

4F0

4F1

VCCQ

VCCN4

4Q1

4Q0

GND

1F0

VCCN1

1Q0

1Q1

GND

SELECT

INPUTS

(THREE

LEVEL)

CY7C9915

SKEW

SELECT

MATRIX

3Q0

3Q1

3F0

3F1

GND

14 15

19 20

2Q0

2Q1

2F0

2F1

1Q0

1Q1

1F0

1F1

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07687 Rev. *A

Revised April 29, 2005

12 3 4 5 6 7...14

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