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CY7C9689-AC

更新时间: 2024-11-10 21:54:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
48页 962K
描述
TAXI Compatible HOTLink Transceiver

CY7C9689-AC 数据手册

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CY7C9689  
TAXI™ Compatible HOTLink® Transceiver  
improve its serial transmission characteristics. These encoded  
characters are then serialized, converted to NRZI, and output  
from two PECL-compatible differential transmission line driv-  
ers at a bit-rate of either 10 or 20 times the input reference  
clock in 8-bit (or 10-bit bypass) mode, or 12 or 24 times the  
reference clock in 10-bit (or 12-bit bypass) mode.  
Features  
• Second-generation HOTLink® technology  
• AMD™ AM7968/7969 TAXIchip™ compatible  
• 8-bit 4B/5B or 10-bit5B/6B NRZIencoded data transport  
• 10-bit or 12-bit NRZI pre-encoded (bypass) data  
transport  
• Synchronous TTL parallel interface  
• Embedded/Bypassable 256 character Transmit and  
Receive FIFOs  
• 50-to-200 MBaud serial signaling rate  
• Internal PLLs with no external PLL components  
• Dual differential PECL-compatible serial inputs and  
outputs  
• Compatible with fiber-optic modules and copper cables  
• Built-In Self-Test (BIST) for link testing  
• Link Quality Indicator  
• Single +5.0V ±10%supply  
• 100-pin TQFP  
The receive section of the CY7C9689 HOTLink accepts a se-  
rial bit-stream from one of two PECL compatible differential  
line receivers and, using a completely integrated PLL Clock  
Synchronizer, recovers the timing information necessary for  
data reconstruction. The recovered bit stream is converted  
from NRZI to NRZ, deserialized, framed into characters, 4B/5B  
or 5B/6B decoded, and checked for transmission errors. The  
recovered 8- or 10-bit decoded characters are then written to  
an internal Receive FIFO, and presented to the destination  
host system.  
The integrated 4B/5B and 5B/6B encoder/decoder may be by-  
passed (disabled) for systems that present externally encoded  
or scrambled data at the parallel interface. With the encoder  
bypassed, the pre-encoded parallel data stream is converted  
to and from a serial NRZI stream. The embedded FIFOs may  
also be bypassed (disabled) to create a reference-locked seri-  
al transmission link. For those systems requiring even greater  
FIFO storage capability, external FIFOs may be directly cou-  
pled to the CY7C9689 through the parallel interface without  
the need for additional glue-logic.  
Functional Description  
The CY7C9689 HOTLink Transceiver is a point-to-point com-  
munications building block allowing the transfer of data over  
high-speed serial links (optical fiber, balanced, and unbal-  
anced copper transmission lines) at speeds ranging between  
50 and 200 MBaud. The transmit section accepts parallel data  
of selectable widths and converts it to serial data, while the  
receiver section accepts serial data and converts it to parallel  
data of selectable widths. Figure 1 illustrates typical connec-  
tions between two independent host systems and correspond-  
ing CY7C9689 parts. The CY7C9689 provides enhanced  
technology, increased functionality, a higher level of integra-  
tion, higher data rates, and lower power dissipation over the  
AMD AM7968/7969 TAXIchip products.  
The TTL parallel I/O interface may be configured as either a  
FIFO (configurable for depth expansion through external  
FIFOs) or as a pipeline register extender. The FIFO configura-  
tions are optimized for transport of time-independent (asyn-  
chronous) 8- or 10-bit character-oriented data across a link. A  
Built-In Self-Test (BIST) pattern generator and checker allows  
for testing of the high-speed serial data paths in both the trans-  
mit and receive sections, and across the interconnecting links.  
HOTLink devices are ideal for a variety of applications where  
parallel interfaces can be replaced with high-speed, point-to-  
point serial links. Some applications include interconnecting  
workstations, backplanes, servers, mass storage, and video  
transmission equipment.  
The transmit section of the CY7C9689 HOTLink can be con-  
figured to accept either 8- or 10-bit data characters on each  
clock cycle, and stores the parallel data into an internal syn-  
chronous Transmit FIFO. Data is read from the Transmit FIFO  
and is encoded using embedded 4B/5B or 5B/6B encoders to  
Transmit  
Data  
Data  
Receive  
Serial Link  
Control  
Control  
Status  
CY7C9689  
CY7C9689  
Status  
Serial Link  
Data  
Transmit  
Receive  
Data  
Figure 1. HOTLink System Connections  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
June 14, 2000  

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