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CY7C954DX-AC PDF预览

CY7C954DX-AC

更新时间: 2024-02-08 20:24:35
品牌 Logo 应用领域
其他 - ETC 异步传输模式ATM
页数 文件大小 规格书
43页 811K
描述
ATM/SONET Transceiver

CY7C954DX-AC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP, QFP100,.63SQ,20
针数:100Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:8.82
应用程序:ATM;SONETJESD-30 代码:S-PQFP-G100
JESD-609代码:e0长度:14 mm
功能数量:1端子数量:100
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 V认证状态:Not Qualified
座面最大高度:1.6 mm子类别:ATM/SONET/SDH ICs
最大压摆率:0.25 mA标称供电电压:5 V
表面贴装:YES技术:CMOS
电信集成电路类型:ATM/SONET/SDH TRANSCEIVER温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:14 mm
Base Number Matches:1

CY7C954DX-AC 数据手册

 浏览型号CY7C954DX-AC的Datasheet PDF文件第2页浏览型号CY7C954DX-AC的Datasheet PDF文件第3页浏览型号CY7C954DX-AC的Datasheet PDF文件第4页浏览型号CY7C954DX-AC的Datasheet PDF文件第5页浏览型号CY7C954DX-AC的Datasheet PDF文件第6页浏览型号CY7C954DX-AC的Datasheet PDF文件第7页 
54DX  
CY7C954DX  
ATM HOTLink® Transceiver  
technology, functionality, and integration over the field proven  
CY7B923/933 HOTLink.  
Features  
• Second-generation HOTLink® technology  
The transmit section of the CY7C954DX HOTLink has been  
configured to accept 8-bit data characters on each clock cycle,  
and store the parallel data into an internal Transmit FIFO. Data  
is read from the Transmit FIFO and is encoded using an em-  
bedded 8B/10B encoder to improve its serial transmission  
characteristics. These encoded characters are then serialized  
and output from two Pseudo ECL (ECL referenced to +5.0V)  
compatible differential transmission line drivers at a bit-rate of  
10 times the input reference clock.  
• UTOPIA level I and II compatible host bus interface  
• Three-bit Multi-PHY address capability built-in  
• Three user-selectable Start Of Cell marker/indicators  
• Embedded 256-character synchronous FIFOs  
• Built-in ATM Header Error Control (HEC)  
• Automatic Transmit-HEC insertion & Receiver-HEC  
check  
• FIFO cell-level flushing of invalid ATM cells  
The receive section of the CY7C954DX HOTLink accepts a  
serial bit-stream from one of two PECL-compatible differential  
line receivers and, using a completely integrated PLL Clock  
Synchronizer, recovers the timing information necessary for  
data reconstruction. The recovered bit stream is deserialized  
and framed into characters, 8B/10B decoded, and checked for  
transmission errors. Recovered decoded characters are re-  
constructed into 8-bit data characters, written to an internal  
Receive FIFO, and presented to the destination host system.  
ATM Forum, Fibre Channel, and ESCON® compliant  
8B/10B encoder/decoder  
• 50- to 200-MBaud serial signaling rate  
• Internal PLLs with no external PLL components  
• Dual differential PECL-compatible serial inputs  
• Dual differential PECL-compatible serial outputs  
• Compatible with fiber-optic modules and copper cables  
• Built-In Self-Test (BIST) for link testing  
• Link Quality Indicator  
For those systems requiring even greater FIFO storage capa-  
bility, external FIFOs may be directly coupled to the  
CY7C954DX device through the parallel interface without ad-  
ditional glue-logic for single PHY connections.  
• Single +5.0V ±10% supply  
• 100-pin TQFP  
• 0.35µ CMOS technology  
The TTL parallel I/O interface may be configured as either a  
FIFO (configurable for UTOPIA emulation or for depth expan-  
sion through external FIFOs) or as a pipeline register extender.  
The FIFO configurations are optimized for transport of time-  
independent (asynchronous) 8-bit character-oriented data  
across a link. A Built-In Self-Test (BIST) pattern generator and  
checker allows for at-speed testing of the high-speed serial  
data paths in both the transmit and receive sections, and  
across the interconnecting links.  
Functional Description  
The 200-MBaud CY7C954DX HOTLink Transceiver is a point-  
to-point communications building block allowing the transfer of  
data over high-speed serial links (optical fiber, balanced, and  
unbalanced copper transmission lines) at speeds ranging be-  
tween 50 and 200 MBaud. The transmit section accepts par-  
allel data of selectable width and converts it to serial data,  
while the receiver section accepts serial data and converts it  
to parallel data of selectable width. Figure 1 illustrates typical  
connections between two independent host systems and cor-  
responding CY7C954DX parts. As a second-generation  
HOTLink device, the CY7C954DX provides enhanced levels of  
HOTLink devices are ideal for a variety of applications where  
parallel interfaces can be replaced with high-speed, point-to-  
point serial links. Some applications include interconnecting  
workstations, backplanes, servers, mass storage, and video  
transmission equipment.  
Transmit  
Data  
Data  
Receive  
Serial Link  
Control  
Control  
Status  
CY7C954DX  
CY7C954DX  
Status  
Serial Link  
Data  
Transmit  
Receive  
Data  
Figure 1. HOTLink System Connections  
HOTLink is a registered trademark of Cypress Semiconductor Corporation.  
ESCON is a registered trademark of International Business Machines.  
Cypress Semiconductor Corporation  
Document #: 38-02007 Rev. **  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Revised June 10, 2000  

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