CONFIDENTIAL
CY7C9538
OC-48/STM-16 Framer with Reconfigurable
VC–POSIC2GVC-R™
• Programmable frame tagging engine for packet
preclassification enables such features as
Features
• OC-48/STS-48/STM-16, OC-12/STS-12/STM-4,
OC-3/STS3/STM-1rates, concatenatedandnon-concat-
enated
— MPLS label lookup and tagging
— PPP: LCP and NCP tagging
— PPP control packets optionally sent to host CPU
interface
• Complies with ITU-Standards G.707/Y.1322 and
G.783[1,2]
• Complies with Bellcore GR253 rev.1, 1997[3]
— MAC/layer 3 address look-up and tagging
• ProgrammableA1A2processingbypassinRxdirection
with frame sync input
• Channelized operation: supports 16xSTS-3c,
4xSTS-12c, 2xSTS-24c, and 1xOC-48c within OC-48
stream
• Complete section overhead (SOH), line overhead
(LOH), and path overhead (POH) processing
• Supports choice of TUG3 or AUG3 mapping for
STS1/VC3 into STS-3c/VC4 tributaries
• APS extraction, CPU interrupt generation, and
programmable insertion of APS byte
• Virtual concatenation enables secure and dedicated
bandwidth provisioning[4]
• Line side APS port interface
• Dynamic reconfiguration of VC bandwidth
• Provision for protection switching on SONET/SDH port
• Programmable PRBS generator and receiver
• Number of active channels can be changed dynami-
cally
• Serial port to access line/section data communication
channel (DCC) and voice communication channel
(VCC)
• Supports dynamic reassignment of transmitted VC
tributaries using slot programming
• Up to 16 channels
• Full duplex OIF-SPI (POS-PHY)/UTOPIA level 3
interface[14,15]
• Allows unused line bandwidth to be unassigned to any
channel
• 16-bit/32-bit host CPU interface bus
• JTAG and boundary scan
• From 50-Mbps to 1.2-Gbps bandwidth per channel
• STS-1 and STS-3c granularity
• Glueless interface with Cypress CYS25G0101DX
OC-48 PHY
• Full duplex mapping of ATM cells over SONET/SDH
• Complies with ITU-Standards I 432.2[5,6,7]
• 0.18-um CMOS, 504-pin BGA package
• Full duplex mapping of packet-over-SONET/SDH: IETF
RFC 1619/1662/2615 (HDLC/PPP)[8,9,10]
• +1.8V for core, +3.3V for LVTTL I/O, +1.5V/+3.3V for
HSTL/LVPECL I/O supply, and +0.75V/2.0V reference
• Generic Framing Procedure (GFP) per ANSI
T1X1.5[11,12,13] Protocol Encapsulator/Decapsulator
delineates GFP frames with length-CRC frame
construct
Applications
• Multiservice nodes
• GFP 268r1
• ATM switches and routers
• User-programmable encapsulation
• User-programmable clear channel transport
• User-programmable SONET/SDH bypass
Notes:
• Packet routers and multiservice routers
• SONET/SDH/Add-Drop Mux for packet/data applications
• SONET/SDH/ATM/POS test equipment
1. ITU-T Recommendation G.707. “Network Node Interface for the Synchronous Digital Hierarchy.” 1996.
2. ITU-T Recommendation G.783. “Characteristics of Synchronous Digital Hierarchy (SDH) Equipment Functional Blocks.” 2000.
3. Bellcore Publication GR-253-Core. “Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria.” 1997.
4. Jones, N., Lucent Microelectronics, and C. Murton, Nortel Networks. “Extending PPP over SONET/DSH with Virtual Concatenation, High-Order and Low-Order
payloads.” Internet Draft. June 2000.
5. ITU-T Recommendation I.432.3. “B-ISDN User-Network Interface—Physical Layer Specification: 1544 kbit/s and 2048 kbit/s Operation.” 1999.
6. American National Standards Institute. “Synchronous Optical Network (SONET)—Basic Description Including Multiplex Structure, Rates and Formats.” ANSI
T1.105-1995.
7. American National Standards Institute. “Synchronous Optical Network (SONET)—Payload Mappings.” ANSI T1.105.02–1998.
8. Simpson, W. “PPP over SONET/SDH.” RFC 1619. May 1994.
9. Simpson, W., ed. “PPP in HDLC-like Framing,” RFC 1662. Daydreamer. July 1994.
10. Malis, A. and W. Simpson. “PPP over SONET/SDH,” RFC 2615. June 1999.
11. Hernandez-Valencia, E., Lucent Technologies. “A Generic Frame Format for Data over SONET (DoS).” March 2000.
12. Gorshe, C. and Steven. T1X1.5/99-204, T1 105.02. Draft Text for Mapping IEEE 802.3 Ethernet MAC Frames to SONET Payload. July 1999.
13. Hernandez-Valencia, E., Lucent Technologies. T1X1.5/2000-209. “Generic Framing Procedure (GFP) Specification.” October 9–13, 2000.
14. ATM Forum, Technical Committee. UUTOPIA 3 Physical Layer Interface.” Af-phy-0136.000. November 1999.
15. Can, R. and R. Tuck. “System Packet Interface Level 3 (SPI-3): OC-48 System Interface for Physical and Link-Layer Devices.” OIF-SPI3-01.0. June 2000.
Cypress Semiconductor Corporation
Document #: 38-02095 Rev. *B
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
RevisedFebruary7, 2005
5秒后页面跳转
全球首块英伟达H200交付 黄仁勋“送货上门”
常用8脚开关电源芯片型号大全
74HC04芯片引脚图及功能、应用电路图讲解
CR6842芯片参数、引脚配置、应用电路图详解
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
